diff options
| author | Bo Kim <bok@nvidia.com> | 2011-08-17 15:52:12 +0900 |
|---|---|---|
| committer | Niket Sirsi <nsirsi@nvidia.com> | 2011-08-17 15:58:13 -0700 |
| commit | e1fefd8a7fb9751ddfad95e469666f3c876123a8 (patch) | |
| tree | 8611ed11a35aa644180b8ac20eacc8cb399e6a26 | |
| parent | f537c37a7daa92e2a6da13e82513f114b0e9a2f7 (diff) | |
ARM: tegra: clock: tegra2_pll_clk_set_rate() process p field is greater then 2.
This change makes tegra2_pll_clk_set_rate() will process for p field is greater
then 2. It helps to increase VCO.
Bug 852217
Bug 842032
Change-Id: I9ad1483521126a52318bd5b641cfe34e0b66ebff
Reviewed-on: http://git-master/r/47492
Reviewed-by: Bo Kim <bok@nvidia.com>
Tested-by: Bo Kim <bok@nvidia.com>
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Gabby Lee <galee@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
| -rw-r--r-- | arch/arm/mach-tegra/tegra2_clocks.c | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c index 4f58d8276fa7..8ffd816a78e7 100644 --- a/arch/arm/mach-tegra/tegra2_clocks.c +++ b/arch/arm/mach-tegra/tegra2_clocks.c @@ -739,13 +739,25 @@ static int tegra2_pll_clk_set_rate(struct clk *c, unsigned long rate) PLL_BASE_DIVM_MASK); val |= (sel->m << PLL_BASE_DIVM_SHIFT) | (sel->n << PLL_BASE_DIVN_SHIFT); - BUG_ON(sel->p < 1 || sel->p > 2); + BUG_ON(sel->p < 1 || sel->p > 128); if (c->flags & PLLU) { if (sel->p == 1) val |= PLLU_BASE_POST_DIV; } else { if (sel->p == 2) val |= 1 << PLL_BASE_DIVP_SHIFT; + else if (sel->p == 4) + val |= 2 << PLL_BASE_DIVP_SHIFT; + else if (sel->p == 8) + val |= 3 << PLL_BASE_DIVP_SHIFT; + else if (sel->p == 16) + val |= 4 << PLL_BASE_DIVP_SHIFT; + else if (sel->p == 32) + val |= 5 << PLL_BASE_DIVP_SHIFT; + else if (sel->p == 64) + val |= 6 << PLL_BASE_DIVP_SHIFT; + else if (sel->p == 128) + val |= 7 << PLL_BASE_DIVP_SHIFT; } clk_writel(val, c->reg + PLL_BASE); |