diff options
| author | Prashant Gaikwad <pgaikwad@nvidia.com> | 2011-07-22 15:06:49 +0530 |
|---|---|---|
| committer | Manish Tuteja <mtuteja@nvidia.com> | 2011-07-25 10:32:26 -0700 |
| commit | 672d1704921e7c6e180416445dd8e86df76db1a2 (patch) | |
| tree | c057f2c100609b674e3257be19d82dabb8450862 | |
| parent | caa12c3b3d1aac557599313be83fbd8715cc7694 (diff) | |
tegra: clock: Add WAR for AP25 EMC scaling
AP25 EMC scaling ladder is 23.75/63.33/95/190/380.
Device will freeze when clock rate is changed from < 95 to 380.
WAR added: Set clock rate to 190 first and then required clock rate.
Bug 821534
Change-Id: Idfd12bdba72e2918dfe0b59c5c54d02b87ec73ea
Reviewed-on: http://git-master/r/41720
Reviewed-by: Manish Tuteja <mtuteja@nvidia.com>
Tested-by: Manish Tuteja <mtuteja@nvidia.com>
| -rw-r--r-- | arch/arm/mach-tegra/tegra2_clocks.c | 17 |
1 files changed, 16 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c index 95b7a9cbc7a1..a48baf9c8d35 100644 --- a/arch/arm/mach-tegra/tegra2_clocks.c +++ b/arch/arm/mach-tegra/tegra2_clocks.c @@ -151,6 +151,8 @@ #define PMC_BLINK_TIMER_DATA_OFF_SHIFT 16 #define PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff +#define AP25_EMC_BRIDGE_RATE 380000000 + static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE); static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE); @@ -1306,7 +1308,9 @@ static struct clk_ops tegra_cdev_clk_ops = { static void tegra2_clk_shared_bus_update(struct clk *bus) { struct clk *c; + unsigned long old_rate; unsigned long rate = bus->min_rate; + int sku_id = tegra_sku_id(); list_for_each_entry(c, &bus->shared_bus_list, u.shared_bus_user.node) { @@ -1314,7 +1318,18 @@ static void tegra2_clk_shared_bus_update(struct clk *bus) rate = max(c->u.shared_bus_user.rate, rate); } - if (rate != clk_get_rate_locked(bus)) + old_rate = clk_get_rate_locked(bus); + + /* WAR: For AP25 EMC scaling */ + if ((sku_id == 0x17) && (bus->flags & PERIPH_EMC_ENB)) { + if (((old_rate > AP25_EMC_BRIDGE_RATE) && + (rate < AP25_EMC_BRIDGE_RATE)) || + ((old_rate < AP25_EMC_BRIDGE_RATE) && + (rate > AP25_EMC_BRIDGE_RATE))) + clk_set_rate_locked(bus, AP25_EMC_BRIDGE_RATE); + } + + if (rate != old_rate) clk_set_rate_locked(bus, rate); }; |