diff options
| author | Joseph Lehrer <jlehrer@nvidia.com> | 2011-06-22 13:58:28 -0700 |
|---|---|---|
| committer | Rohan Somvanshi <rsomvanshi@nvidia.com> | 2011-06-24 05:46:54 -0700 |
| commit | fe183103486468746b63729f502ed732065a0134 (patch) | |
| tree | 6f95ad45276e207ea885b1c32858b107f4038d90 | |
| parent | e2d0f09b2177cedaad92b10920bc890202c7e095 (diff) | |
video: tegra: add 504MHz pll_d rate for HDMI
To support the 25.2MHz pixel clock frequency required for CEA-861-B format 1: 640x480p at 59.94Hz
bug 837571
Change-Id: I33d5c82bbc9c79fd43d86abf72d5b94b1c723dd5
Reviewed-on: http://git-master/r/37916
Reviewed-by: Joseph Lehrer <jlehrer@nvidia.com>
Tested-by: Joseph Lehrer <jlehrer@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
| -rw-r--r-- | drivers/video/tegra/dc/dc.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/video/tegra/dc/dc.c b/drivers/video/tegra/dc/dc.c index 9d1bc8188162..c401562694cb 100644 --- a/drivers/video/tegra/dc/dc.c +++ b/drivers/video/tegra/dc/dc.c @@ -732,10 +732,14 @@ void tegra_dc_setup_clk(struct tegra_dc *dc, struct clk *clk) struct clk *pll_d_clk = clk_get_sys(NULL, "pll_d"); + /* needs to match tegra_dc_hdmi_supported_modes[] + and tegra_pll_d_freq_table[] */ if (dc->mode.pclk > 70000000) rate = 594000000; - else + else if (dc->mode.pclk > 25200000) rate = 216000000; + else + rate = 504000000; if (rate != clk_get_rate(pll_d_clk)) clk_set_rate(pll_d_clk, rate); |