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authorAllen Xu <b45815@freescale.com>2014-12-10 06:12:00 +0800
committerAllen Xu <b45815@freescale.com>2014-12-10 23:45:39 +0800
commitb4dbaacb12b6cee20baf6effa8bcf37b7309fb24 (patch)
treeadceb8e51b39a2012c03de6139b931b51120568d
parent39283bfa752053b1d62484c42aa2239d6aafe2ae (diff)
MLK-9976: ARM: dts: NAND BBT inconsistency causes UBIFS randomly mount failed
NAND scans the bad blocks during kernel boots up, which invokes the gpmi_ecc_read_oob function to check the badblock mark for each block. In this function the oob data was raw read from NAND chip without ECC, so it hardly to guarantee the consistency of the data considering the possible bitflips. It found that in some MLC NAND the oob data changed and consequently the BBT changed in different power cycles. This issue may cause the UBIFS mount failed. To fix this issue, add "nand_on_flash_bbt" option in dts to store the BBT in NAND flash. On the first time kernel boot up, all bad blocks and probably some fake bad block would be recognized and be recorded in on-nand bad block table. From the second time boot, kernel will read BBT from NAND Flash rather than calling gpmi_ecc_read_oob function to check bad block. No bad block would be missed when create BBT since the probability that 16bit bad block mark filps from 0x00 to 0xFF is extremely low. Signed-off-by: Allen Xu <b45815@freescale.com> (cherry picked from commit d957353768a1b6d39b340b9d10b22fc42b0aa8e2)
-rw-r--r--arch/arm/boot/dts/imx6q-arm2.dts1
-rw-r--r--arch/arm/boot/dts/imx6qdl-sabreauto.dtsi1
-rw-r--r--arch/arm/boot/dts/imx6sx-17x17-arm2-gpmi-weim.dts1
-rw-r--r--arch/arm/boot/dts/imx6sx-17x17-arm2.dts1
-rw-r--r--arch/arm/boot/dts/imx6sx-19x19-arm2-gpmi-weim.dts1
-rw-r--r--arch/arm/boot/dts/imx6sx-sabreauto.dts1
6 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts
index e6ad9546e852..8326f1a8d930 100644
--- a/arch/arm/boot/dts/imx6q-arm2.dts
+++ b/arch/arm/boot/dts/imx6q-arm2.dts
@@ -73,6 +73,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand_1>;
status = "disabled"; /* gpmi nand conflicts with SD */
+ nand-on-flash-bbt;
};
&iomuxc {
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index fc6934d344c7..3a9fcb50322d 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -687,6 +687,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand_1>;
status = "disabled"; /* pin conflict with uart3 */
+ nand-on-flash-bbt;
};
&uart4 {
diff --git a/arch/arm/boot/dts/imx6sx-17x17-arm2-gpmi-weim.dts b/arch/arm/boot/dts/imx6sx-17x17-arm2-gpmi-weim.dts
index 13b62024f8eb..3a9d8e3dc61c 100644
--- a/arch/arm/boot/dts/imx6sx-17x17-arm2-gpmi-weim.dts
+++ b/arch/arm/boot/dts/imx6sx-17x17-arm2-gpmi-weim.dts
@@ -190,6 +190,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand_1>;
status = "okay"; /* pin conflict with qspi*/
+ nand-on-flash-bbt;
};
&i2c1 {
diff --git a/arch/arm/boot/dts/imx6sx-17x17-arm2.dts b/arch/arm/boot/dts/imx6sx-17x17-arm2.dts
index 0fcc8fbfd088..51e2b0d439bd 100644
--- a/arch/arm/boot/dts/imx6sx-17x17-arm2.dts
+++ b/arch/arm/boot/dts/imx6sx-17x17-arm2.dts
@@ -197,6 +197,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand_1>;
status = "disabled"; /* pin conflict with qspi*/
+ nand-on-flash-bbt;
};
&i2c1 {
diff --git a/arch/arm/boot/dts/imx6sx-19x19-arm2-gpmi-weim.dts b/arch/arm/boot/dts/imx6sx-19x19-arm2-gpmi-weim.dts
index 7a6919600a44..9237f157876d 100644
--- a/arch/arm/boot/dts/imx6sx-19x19-arm2-gpmi-weim.dts
+++ b/arch/arm/boot/dts/imx6sx-19x19-arm2-gpmi-weim.dts
@@ -456,6 +456,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand_1>;
status = "okay"; /* pin conflict with qspi*/
+ nand-on-flash-bbt;
};
&qspi2 {
diff --git a/arch/arm/boot/dts/imx6sx-sabreauto.dts b/arch/arm/boot/dts/imx6sx-sabreauto.dts
index 23ea6f01ac95..ba30c90ce233 100644
--- a/arch/arm/boot/dts/imx6sx-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6sx-sabreauto.dts
@@ -658,6 +658,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand_1>;
status = "okay";
+ nand-on-flash-bbt;
};
&vadc {