diff options
| author | Ye.Li <B37916@freescale.com> | 2014-12-01 17:28:47 +0800 |
|---|---|---|
| committer | Ye.Li <B37916@freescale.com> | 2014-12-01 18:58:48 +0800 |
| commit | 9953eb70c1337e1003fe44e20a2a76fc1c63716a (patch) | |
| tree | 001213d95c813a710845f94fd124018c460c4038 | |
| parent | 25f48e7517e7561deb3d50e8590284a4c5e63c2c (diff) | |
MLK-9920 mtd: qspi: Add ddrsmp parameter to device tree
Since QSPI internal DDR sample point is relevant with board layout,
we can't use same value for all boards. Add ddrsmp parameter to device
tree for i.MX6SX Sabreauto/Sabresd board.
DDRSMP value:
0 ---- i.MX6SX Sabresd board (RevB and RevA)
2 ---- i.MX6SX Sabreauto board
The Sabresd RevA board also needs to reduce clock to 29Mhz according to
the Spansion spec.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit c9115cc22d836b5b980ca20932a005ea61b20082)
| -rw-r--r-- | arch/arm/boot/dts/imx6sx-sabreauto.dts | 1 | ||||
| -rw-r--r-- | arch/arm/boot/dts/imx6sx-sdb-reva.dts | 5 | ||||
| -rw-r--r-- | arch/arm/boot/dts/imx6sx-sdb.dts | 2 | ||||
| -rw-r--r-- | drivers/mtd/spi-nor/fsl-quadspi.c | 10 |
4 files changed, 15 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/imx6sx-sabreauto.dts b/arch/arm/boot/dts/imx6sx-sabreauto.dts index 59f305d510c4..23ea6f01ac95 100644 --- a/arch/arm/boot/dts/imx6sx-sabreauto.dts +++ b/arch/arm/boot/dts/imx6sx-sabreauto.dts @@ -635,6 +635,7 @@ /* only map 128MB */ reg = <0x021e0000 0x4000>, <0x60000000 0x8000000>; status = "okay"; + ddrsmp=<2>; flash0: n25q256a@0 { #address-cells = <1>; diff --git a/arch/arm/boot/dts/imx6sx-sdb-reva.dts b/arch/arm/boot/dts/imx6sx-sdb-reva.dts index 1107e3497185..330810550f96 100644 --- a/arch/arm/boot/dts/imx6sx-sdb-reva.dts +++ b/arch/arm/boot/dts/imx6sx-sdb-reva.dts @@ -65,12 +65,13 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_qspi2_1>; status = "okay"; + ddrsmp=<0>; flash0: s25fl128s@0 { #address-cells = <1>; #size-cells = <1>; compatible = "spansion,s25fl128s"; - spi-max-frequency = <66000000>; + spi-max-frequency = <29000000>; reg = <0>; }; @@ -78,7 +79,7 @@ #address-cells = <1>; #size-cells = <1>; compatible = "spansion,s25fl128s"; - spi-max-frequency = <66000000>; + spi-max-frequency = <29000000>; reg = <1>; }; }; diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts index 02c99958fed2..6d7a66ebc39d 100644 --- a/arch/arm/boot/dts/imx6sx-sdb.dts +++ b/arch/arm/boot/dts/imx6sx-sdb.dts @@ -681,6 +681,8 @@ status = "okay"; #ifndef SPANSIONFLASH + ddrsmp=<0>; + flash0: n25q256a@0 { #address-cells = <1>; #size-cells = <1>; diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c index 980c6173edec..8a4997a3dcc4 100644 --- a/drivers/mtd/spi-nor/fsl-quadspi.c +++ b/drivers/mtd/spi-nor/fsl-quadspi.c @@ -240,6 +240,7 @@ struct fsl_qspi { u32 clk_rate; unsigned int chip_base_addr; /* We may support two chips. */ bool ddr_io_mode; + u32 ddr_smp; struct mutex lock; }; @@ -673,7 +674,8 @@ static void fsl_qspi_init_abh_read(struct fsl_qspi *q) /* Set the Sampling Register for DDR */ reg2 = readl(q->iobase + QUADSPI_SMPR); reg2 &= ~QUADSPI_SMPR_DDRSMP_MASK; - reg2 |= (2 << QUADSPI_SMPR_DDRSMP_SHIFT); + reg2 |= ((q->ddr_smp << QUADSPI_SMPR_DDRSMP_SHIFT) & + QUADSPI_SMPR_DDRSMP_MASK); writel(reg2, q->iobase + QUADSPI_SMPR); /* Enable the module again (enable the DDR too) */ @@ -975,6 +977,12 @@ static int fsl_qspi_probe(struct platform_device *pdev) goto map_failed; } + /* find ddrsmp value */ + ret = of_property_read_u32(dev->of_node, "ddrsmp", + &q->ddr_smp); + if (ret) + q->ddr_smp = 0; + ret = fsl_qspi_clk_prep_enable(q); if (ret) { dev_err(dev, "can not enable the clock\n"); |