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authorRanjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>2014-07-11 16:12:18 -0500
committerRanjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>2014-07-14 08:53:01 -0500
commit9168b9154cf97a9c9c367eb639e92a10f3382144 (patch)
tree825777bba418cdc193ddc277d73438d8b8c7bdec
parent468497ef1ec99087200799d22ef47a97a3d5583a (diff)
ENGR00322563 ARM:imx6sl:Ensure that the CPU frequency is maintianed at 396MHz in low power idle.
In low power IDLE mode, CPU needs to be sourced from PLL1 instead of PLL2_PFD0 as PLL2 needs to be in bypass mode to achieve 24MHz DDR frequency. The original code attempts to relock the PLL1 at frequency that is as close as possible to 396MHz, which results in PLL1 at 648MHz and the ARM freq turns out to be 324MHz instead of 396MHz. This causes issues with CPUFREQ as 324MHz is not a frequency listed in the cpufreq table in the device tree. This patch attempts to fix this mis-match and maintains CPU freq at 396MHz in low power idle. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
-rw-r--r--arch/arm/mach-imx/busfreq-imx6.c9
1 files changed, 7 insertions, 2 deletions
diff --git a/arch/arm/mach-imx/busfreq-imx6.c b/arch/arm/mach-imx/busfreq-imx6.c
index d4529ab490ea..12e8f69ee935 100644
--- a/arch/arm/mach-imx/busfreq-imx6.c
+++ b/arch/arm/mach-imx/busfreq-imx6.c
@@ -268,11 +268,16 @@ static void enter_lpm_imx6sl(void)
* we need to move ARM clk off PLL2_PFD2
* to PLL1. Make sure the PLL1 is running
* at the lowest possible freq.
+ * To work well with CPUFREQ we want to ensure that
+ * the CPU freq does not change, so attempt to
+ * get a freq as close to 396MHz as possible.
*/
clk_set_rate(pll1_sys,
- clk_round_rate(pll1_sys, org_arm_rate));
+ clk_round_rate(pll1_sys, (org_arm_rate * 2)));
pll1_rate = clk_get_rate(pll1_sys);
- arm_div = pll1_rate / org_arm_rate + 1;
+ arm_div = pll1_rate / org_arm_rate;
+ if (pll1_rate / arm_div > org_arm_rate)
+ arm_div++;
/*
* Ensure ARM CLK is lower before
* changing the parent.