diff options
| author | Dong Aisheng <b29396@freescale.com> | 2013-11-22 13:45:22 +0800 |
|---|---|---|
| committer | Dong Aisheng <b29396@freescale.com> | 2013-11-22 15:50:14 +0800 |
| commit | c3c39b6b7034d47f3b6f42933598bcd9466f2539 (patch) | |
| tree | 2acb798db365b02921166647ae85ca0ecd89a675 | |
| parent | 8345287f4f634094dd26d9e1e3c313598b404de3 (diff) | |
ENGR00289278 dts: imx6qdl-sabreauto: fix usdhc1 pin conflict with gpmi
The SD1 on sabreauto baseboard is conflict with gpmi nand. The conflict
pins are DAT4~DAT7. Since the SD3 on cpu board already supports 8 bit bus
width, we do not want add an extra dts file for it, so we disable 8 bit and use
4 bit width for this issue.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
(cherry picked from commit 92a24bffe9b79787e9881ffc6ede7e5e3df308f7)
| -rw-r--r-- | arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 1 | ||||
| -rw-r--r-- | arch/arm/boot/dts/imx6qdl.dtsi | 4 |
2 files changed, 0 insertions, 5 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index b6a791f7b2e9..a2dd4385c4fe 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -651,7 +651,6 @@ pinctrl-0 = <&pinctrl_usdhc1_1>; cd-gpios = <&gpio1 1 0>; wp-gpios = <&gpio5 20 0>; - bus-width = <8>; no-1-8-v; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 9eb8034480ec..9dd4cbdf6cef 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -1535,10 +1535,6 @@ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 - MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071 - MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071 - MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17071 - MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17071 >; }; }; |