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authorRobby Cai <R63905@freescale.com>2012-10-16 15:53:29 +0800
committerRobby Cai <R63905@freescale.com>2012-10-23 11:06:23 +0800
commit812dd3a5790b6def3919d82ca07f873c8618d454 (patch)
tree5ada5be73460125d3c6e82a7500ea53afb82cfc6
parent980295f7fe015ed89671e4d73397c11a006b8b4c (diff)
ENGR00229785 pgc: disable display power gating when FB_MXC_ELCDIF_FB configured
Only enable power gating for PXP and EPDC. The feature for ELCDIF still need to be verified. Signed-off-by: Robby Cai <R63905@freescale.com>
-rw-r--r--arch/arm/mach-mx6/pm.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/mach-mx6/pm.c b/arch/arm/mach-mx6/pm.c
index b29c6f6ab0d3..654881af57bd 100644
--- a/arch/arm/mach-mx6/pm.c
+++ b/arch/arm/mach-mx6/pm.c
@@ -178,6 +178,8 @@ static void usb_power_up_handler(void)
static void disp_power_down(void)
{
+#if !defined(CONFIG_FB_MXC_ELCDIF_FB) && \
+ !defined(CONFIG_FB_MXC_ELCDIF_FB_MODULE)
if (cpu_is_mx6sl()) {
__raw_writel(0xFFFFFFFF, gpc_base + GPC_PGC_DISP_PUPSCR_OFFSET);
__raw_writel(0xFFFFFFFF, gpc_base + GPC_PGC_DISP_PDNSCR_OFFSET);
@@ -194,10 +196,13 @@ static void disp_power_down(void)
~MXC_CCM_CCGRx_CG1_MASK, MXC_CCM_CCGR3);
}
+#endif
}
static void disp_power_up(void)
{
+#if !defined(CONFIG_FB_MXC_ELCDIF_FB) && \
+ !defined(CONFIG_FB_MXC_ELCDIF_FB_MODULE)
if (cpu_is_mx6sl()) {
/*
* Need to enable EPDC/LCDIF pix clock, and
@@ -214,6 +219,7 @@ static void disp_power_up(void)
__raw_writel(0x20, gpc_base + GPC_CNTR_OFFSET);
__raw_writel(0x1, gpc_base + GPC_PGC_DISP_SR_OFFSET);
}
+#endif
}
static void mx6_suspend_store(void)