diff options
| author | Ranjani Vaidyanathan <ra5478@freescale.com> | 2012-08-29 14:38:03 -0500 |
|---|---|---|
| committer | Jason Liu <r64343@freescale.com> | 2012-09-05 13:12:32 +0800 |
| commit | 963285ae38077768f0e342e00e246a64abd8f315 (patch) | |
| tree | a69ed32bec8817ab86f98183c4185bcc701d4f28 | |
| parent | 0328cb1a7c54cef123e2558d66ccf427a9ac99d8 (diff) | |
ENGR00221970 MX6SL:Fix suspend/resume issue on MX6SLEVK
Make sure the Pull Ups are enabled on the DQS lines of
LPDDR2 memory. Without that its possible that the data
latched by the memory will be incorrect when exiting from
self-refresh mode. So only set the drive strengths to 0
when floating the DDR IO pads before entering suspend.
Also never float the CKE pad, this pin always needs to be
driven, else the DDR may incorrectly exit self-refresh.
Hence remove the line that was setting CKE drive strength
to zero (GRP_CTLDS).
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
| -rw-r--r-- | arch/arm/mach-mx6/mx6_suspend.S | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/arch/arm/mach-mx6/mx6_suspend.S b/arch/arm/mach-mx6/mx6_suspend.S index 59b676038427..a9b7e30cd85a 100644 --- a/arch/arm/mach-mx6/mx6_suspend.S +++ b/arch/arm/mach-mx6/mx6_suspend.S @@ -85,8 +85,7 @@ r2: suspend_iram_base ldr r4, [r1, #0x330] /* DRAM_SDCKE0 */ ldr r5, [r1, #0x334] /* DRAM_SDCKE1 */ ldr r6, [r1, #0x320] /* DRAM_RESET */ - ldr r7, [r1, #0x5c8] /* GPR_CTLDS */ - stmfd r0!, {r4-r7} + stmfd r0!, {r4-r6} .endm @@ -122,11 +121,10 @@ r2: suspend_iram_base str r6, [r1, #0x33c] /* DRAM_SODT0*/ str r7, [r1, #0x340] /* DRAM_SODT1*/ - ldmea r0!, {r4-r7} + ldmea r0!, {r4-r6} str r4, [r1, #0x330] /* DRAM_SDCKE0 */ str r5, [r1, #0x334] /* DRAM_SDCKE1 */ str r6, [r1, #0x320] /* DRAM_RESET */ - str r7, [r1, #0x5c8] /* GPR_CTLDS */ .endm @@ -138,6 +136,13 @@ r2: suspend_iram_base str r0, [r1, #0x314] /* DRAM_DQM2 */ str r0, [r1, #0x318] /* DRAM_DQM3 */ + /* Make sure the Pull Ups are enabled. + * So only reduce the drive stength, but + * leave the pull-ups in the original state. + * This is required for LPDDR2. + */ + ldr r0, [r1, #0x344] + orr r0, r0, #0x3000 str r0, [r1, #0x344] /* DRAM_SDQS0 */ str r0, [r1, #0x348] /* DRAM_SDQS1 */ str r0, [r1, #0x34c] /* DRAM_SDQS2 */ @@ -158,7 +163,6 @@ r2: suspend_iram_base str r0, [r1, #0x33c] /* DRAM_SODT0*/ str r0, [r1, #0x340] /* DRAM_SODT1*/ - str r0, [r1, #0x5c8] /* GPR_CTLDS */ mov r0, #0x80000 str r0, [r1, #0x320] /* DRAM_RESET */ mov r0, #0x1000 |