diff options
| author | Anson Huang <b20788@freescale.com> | 2011-07-25 16:14:24 +0800 |
|---|---|---|
| committer | Anson Huang <b20788@freescale.com> | 2011-07-25 16:21:02 +0800 |
| commit | ad53b52bc8d526e8b2c967d2c12b4040d7e5bb26 (patch) | |
| tree | 7886836b6d7488e21c225970e8483b203c75582f | |
| parent | 591ecdada27d1594aa76a87a67ba80ed0d6300b5 (diff) | |
ENGR00153601 [MX6]Adjust L2 cache parameter
Adjust L2 cache parameter to improve both
performance and power consumption.
Signed-off-by: Anson Huang <b20788@freescale.com>
| -rw-r--r-- | arch/arm/mach-mx6/mm.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/mach-mx6/mm.c b/arch/arm/mach-mx6/mm.c index ab91c38f433e..f1d6d6d76924 100644 --- a/arch/arm/mach-mx6/mm.c +++ b/arch/arm/mach-mx6/mm.c @@ -66,6 +66,18 @@ void __init mx6_map_io(void) #ifdef CONFIG_CACHE_L2X0 static int mxc_init_l2x0(void) { + unsigned int val; + + writel(0x132, IO_ADDRESS(L2_BASE_ADDR + L2X0_TAG_LATENCY_CTRL)); + writel(0x132, IO_ADDRESS(L2_BASE_ADDR + L2X0_DATA_LATENCY_CTRL)); + + val = readl(IO_ADDRESS(L2_BASE_ADDR + L2X0_PREFETCH_CTRL)); + val |= 0x40800000; + writel(val, IO_ADDRESS(L2_BASE_ADDR + L2X0_PREFETCH_CTRL)); + val = readl(IO_ADDRESS(L2_BASE_ADDR + L2X0_POWER_CTRL)); + val |= L2X0_DYNAMIC_CLK_GATING_EN; + val |= L2X0_STNDBY_MODE_EN; + writel(val, IO_ADDRESS(L2_BASE_ADDR + L2X0_POWER_CTRL)); l2x0_init(IO_ADDRESS(L2_BASE_ADDR), 0x0, ~0x00000000); return 0; |