diff options
| author | Danny Nold <dannynold@freescale.com> | 2011-03-31 22:25:52 -0500 |
|---|---|---|
| committer | Danny Nold <dannynold@freescale.com> | 2011-04-07 10:16:34 -0500 |
| commit | 0e3e88e624de24e0a5f2bd3491552f0622db2275 (patch) | |
| tree | 730e5f19fa72b8e0ad1afb9a677e2790a25abeba | |
| parent | 36c4b00496c27b90bb3b0b9d26ba0ce23e5c7a71 (diff) | |
ENGR00140737-2 - ARM: imx50: Fix APLL relocking and remove APLL auto-disable
- Removed setting of pfd_disable_mask bits in pfd enable/disable functions.
This feature, which automates the disabling of the APLL, was being used
incorrectly and is less clear than manually enabling/disabling PFD and
APLL clocks directly.
- Added wait for APLL relocking after APLL is enabled.
Signed-off-by: Danny Nold <dannynold@freescale.com>
| -rw-r--r-- | arch/arm/mach-mx5/clock_mx50.c | 20 |
1 files changed, 5 insertions, 15 deletions
diff --git a/arch/arm/mach-mx5/clock_mx50.c b/arch/arm/mach-mx5/clock_mx50.c index 7c0727a9c0ef..01359035f515 100644 --- a/arch/arm/mach-mx5/clock_mx50.c +++ b/arch/arm/mach-mx5/clock_mx50.c @@ -309,6 +309,11 @@ static struct clk ckil_clk = { static int apll_enable(struct clk *clk) { __raw_writel(1, apll_base + MXC_ANADIG_MISC_SET); + + if (!WAIT(__raw_readl(apll_base + MXC_ANADIG_PLLCTRL) + & MXC_ANADIG_APLL_LOCK, 80000)) + panic("apll_enable failed!\n"); + return 0; } @@ -378,23 +383,10 @@ static int pfd_enable(struct clk *clk) apbh_dma_clk.enable(&apbh_dma_clk); index = _get_mux8(clk, &pfd0_clk, &pfd1_clk, &pfd2_clk, &pfd3_clk, &pfd4_clk, &pfd5_clk, &pfd6_clk, &pfd7_clk); - __raw_writel(1 << (index + MXC_ANADIG_PFD_DIS_OFFSET), - apll_base + MXC_ANADIG_PLLCTRL_CLR); /* clear clk gate bit */ __raw_writel((1 << (clk->enable_shift + 7)), apll_base + (int)clk->enable_reg + 8); - /* check lock bit */ - if (!WAIT(__raw_readl(apll_base + MXC_ANADIG_PLLCTRL) - & MXC_ANADIG_APLL_LOCK, 50000)) { - __raw_writel(MXC_ANADIG_APLL_FORCE_LOCK, - apll_base + MXC_ANADIG_PLLCTRL_CLR); - __raw_writel(MXC_ANADIG_APLL_FORCE_LOCK, - apll_base + MXC_ANADIG_PLLCTRL_SET); - if (!WAIT(__raw_readl(apll_base + MXC_ANADIG_PLLCTRL) - & MXC_ANADIG_APLL_LOCK, SPIN_DELAY)) - panic("pfd_enable failed!\n"); - } if (apbh_dma_clk.usecount == 0) apbh_dma_clk.disable(&apbh_dma_clk); return 0; @@ -411,8 +403,6 @@ static void pfd_disable(struct clk *clk) /* set clk gate bit */ __raw_writel((1 << (clk->enable_shift + 7)), apll_base + (int)clk->enable_reg + 4); - __raw_writel(1 << (index + MXC_ANADIG_PFD_DIS_OFFSET), - apll_base + MXC_ANADIG_PLLCTRL_SET); if (apbh_dma_clk.usecount == 0) apbh_dma_clk.disable(&apbh_dma_clk); } |