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authorXinyu Chen <xinyu.chen@freescale.com>2010-10-19 14:05:46 +0800
committerXinyu Chen <xinyu.chen@freescale.com>2010-10-19 14:05:46 +0800
commitb866451e8c0100877e52874299fa17c30f78387e (patch)
treea0a6e75de783b1c34ca5f8692d4edd73d1159100
parentf3e7e14b77b21f693b91eccfa06981878b67906a (diff)
ENGR00132761 MX51: correct the debug early uart's clock
As uboot changes the PLL1, this causes the UART1 clock PRE/PODF divider settings are not correct. Fix this by set uart's parent to PLL3 as uboot did. Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
-rw-r--r--arch/arm/mach-mx5/clock.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/mach-mx5/clock.c b/arch/arm/mach-mx5/clock.c
index 40ea0130a273..aacb6af1ee78 100644
--- a/arch/arm/mach-mx5/clock.c
+++ b/arch/arm/mach-mx5/clock.c
@@ -4677,8 +4677,8 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long
(0 << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET);
__raw_writel(reg, MXC_CCM_CSCDR1);
} else {
- /* Move UART to run from PLL1 */
- clk_set_parent(&uart_main_clk, &pll1_sw_clk);
+ /* Move UART to run from PLL3 */
+ clk_set_parent(&uart_main_clk, &pll3_sw_clk);
/* Set the UART dividers to divide,
* so the UART_CLK is 66.5MHz.
@@ -4686,8 +4686,8 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long
reg = __raw_readl(MXC_CCM_CSCDR1);
reg &= ~MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
reg &= ~MXC_CCM_CSCDR1_UART_CLK_PRED_MASK;
- reg |= (5 << MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET) |
- (1 << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET);
+ reg |= (3 << MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET) |
+ (0 << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET);
__raw_writel(reg, MXC_CCM_CSCDR1);
}