ENGR00125052-2 Driver modifications when enable the eMMC44 DDR

The driver related codes' modifications
when enable the eMMC44 DDR mode on MX53 EVK board

Signed-off-by: Richard Zhu <r65037@freescale.com>

2 files changed, 92 insertions, 6 deletions

diff --git a/drivers/mmc/host/mx_sdhci.c b/drivers/mmc/host/mx_sdhci.c
index 520310a3354c..def8f0da39fe 100644
--- a/drivers/mmc/host/mx_sdhci.c
+++ b/drivers/mmc/host/mx_sdhci.c
@@ -750,6 +750,11 @@ static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
 		flags |= SDHCI_CMD_DATA;
 
 	mode |= SDHCI_MAKE_CMD(cmd->opcode, flags);
+	if (host->mmc->ios.bus_width & MMC_BUS_WIDTH_DDR) {
+		/* Eanble the DDR mode */
+		mode |= SDHCI_TRNS_DDR_EN;
+	} else
+		mode &= ~SDHCI_TRNS_DDR_EN;
 	DBG("Complete sending cmd, transfer mode would be 0x%x.\n", mode);
 	writel(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
 }
@@ -798,6 +803,7 @@ static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
 	int clk_rate = 0;
 	u32 clk;
 	unsigned long timeout;
+	struct mmc_ios ios = host->mmc->ios;
 
 	if (clock == 0) {
 		goto out;
@@ -807,7 +813,7 @@ static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
 			host->plat_data->clk_flg = 1;
 		}
 	}
-	if (clock == host->clock)
+	if (clock == host->clock && !(ios.bus_width & MMC_BUS_WIDTH_DDR))
 		return;
 
 	clk_rate = clk_get_rate(host->clk);
@@ -843,6 +849,75 @@ static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
 	DBG("prescaler = 0x%x, divider = 0x%x\n", prescaler, div);
 	clk |= (prescaler << 8) | (div << 4);
 
+	/* Configure the DLL when DDR mode is enabled */
+	if (ios.bus_width & MMC_BUS_WIDTH_DDR) {
+		/* Enable the DLL and delay chain */
+		writel(readl(host->ioaddr + SDHCI_DLL_CONTROL)
+				| DLL_CTRL_ENABLE,
+				host->ioaddr + SDHCI_DLL_CONTROL);
+
+		timeout = 1000000;
+		while (timeout > 0) {
+			timeout--;
+			if (readl(host->ioaddr + SDHCI_DLL_STATUS)
+					& DLL_STS_REF_LOCK)
+				break;
+			else if (timeout == 0)
+				printk(KERN_ERR "DLL REF LOCK Timeout!\n");
+		};
+		DBG("dll stat: 0x%x\n", readl(host->ioaddr + SDHCI_DLL_STATUS));
+
+		writel(readl(host->ioaddr + SDHCI_DLL_CONTROL)
+				| DLL_CTRL_SLV_UP_INT | DLL_CTRL_REF_UP_INT,
+				host->ioaddr + SDHCI_DLL_CONTROL);
+
+		writel(readl(host->ioaddr + SDHCI_DLL_CONTROL)
+				| DLL_CTRL_SLV_DLY_TAR,
+				host->ioaddr + SDHCI_DLL_CONTROL);
+
+		timeout = 1000000;
+		while (timeout > 0) {
+			timeout--;
+			if (readl(host->ioaddr + SDHCI_DLL_STATUS)
+					& DLL_STS_SLV_LOCK)
+				break;
+			else if (timeout == 0)
+				printk(KERN_ERR "DLL SLV LOCK Timeout!\n");
+		};
+
+		writel(readl(host->ioaddr + SDHCI_DLL_CONTROL)
+				| DLL_CTRL_SLV_FORCE_UPD,
+				host->ioaddr + SDHCI_DLL_CONTROL);
+
+		writel(readl(host->ioaddr + SDHCI_DLL_CONTROL)
+				& (~DLL_CTRL_SLV_FORCE_UPD),
+				host->ioaddr + SDHCI_DLL_CONTROL);
+
+		timeout = 1000000;
+		while (timeout > 0) {
+			timeout--;
+			if (readl(host->ioaddr + SDHCI_DLL_STATUS)
+					& DLL_STS_REF_LOCK)
+				break;
+			else if (timeout == 0)
+				printk(KERN_ERR "DLL REF LOCK Timeout!\n");
+		};
+		timeout = 1000000;
+		while (timeout > 0) {
+			timeout--;
+			if (readl(host->ioaddr + SDHCI_DLL_STATUS)
+					& DLL_STS_SLV_LOCK)
+				break;
+			else if (timeout == 0)
+				printk(KERN_ERR "DLL SLV LOCK Timeout!\n");
+		};
+		DBG("dll stat: 0x%x\n", readl(host->ioaddr + SDHCI_DLL_STATUS));
+	} else if (readl(host->ioaddr + SDHCI_DLL_STATUS) & DLL_STS_SLV_LOCK) {
+		/* reset DLL CTRL */
+		writel(readl(host->ioaddr + SDHCI_DLL_CONTROL) | DLL_CTRL_RESET,
+				host->ioaddr + SDHCI_DLL_CONTROL);
+	}
+
 	/* Configure the clock control register */
 	clk |=
 	    (readl(host->ioaddr + SDHCI_CLOCK_CONTROL) & (~SDHCI_CLOCK_MASK));
@@ -956,8 +1031,8 @@ static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 	u32 tmp;
 	mxc_dma_device_t dev_id = 0;
 
-	DBG("%s: clock %u, bus %lu, power %u, vdd %u\n", DRIVER_NAME,
-	    ios->clock, 1UL << ios->bus_width, ios->power_mode, ios->vdd);
+	DBG("%s: clock %u, bus %u, power %u, vdd %u\n", DRIVER_NAME,
+	    ios->clock, ios->bus_width, ios->power_mode, ios->vdd);
 
 	host = mmc_priv(mmc);
 
@@ -1023,10 +1098,10 @@ static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 
 	tmp = readl(host->ioaddr + SDHCI_HOST_CONTROL);
 
-	if (ios->bus_width == MMC_BUS_WIDTH_4) {
+	if ((ios->bus_width & ~MMC_BUS_WIDTH_DDR) == MMC_BUS_WIDTH_4) {
 		tmp &= ~SDHCI_CTRL_8BITBUS;
 		tmp |= SDHCI_CTRL_4BITBUS;
-	} else if (ios->bus_width == MMC_BUS_WIDTH_8) {
+	} else if ((ios->bus_width & ~MMC_BUS_WIDTH_DDR) == MMC_BUS_WIDTH_8) {
 		tmp &= ~SDHCI_CTRL_4BITBUS;
 		tmp |= SDHCI_CTRL_8BITBUS;
 	} else if (ios->bus_width == MMC_BUS_WIDTH_1) {
diff --git a/drivers/mmc/host/mx_sdhci.h b/drivers/mmc/host/mx_sdhci.h
index 0bd79934952e..358050501cac 100644
--- a/drivers/mmc/host/mx_sdhci.h
+++ b/drivers/mmc/host/mx_sdhci.h
@@ -2,7 +2,6 @@
  *  linux/drivers/mmc/host/mx_sdhci.h - Secure Digital Host
  *  Controller Interface driver
  *
- *  Copyright (C) 2005-2007 Pierre Ossman, All Rights Reserved.
  *  Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  *
  * This program is free software; you can redistribute it and/or modify
@@ -28,6 +27,7 @@
 #define  SDHCI_TRNS_DMA		0x00000001
 #define  SDHCI_TRNS_BLK_CNT_EN	0x00000002
 #define  SDHCI_TRNS_ACMD12	0x00000004
+#define  SDHCI_TRNS_DDR_EN 	0x00000008
 #define  SDHCI_TRNS_READ	0x00000010
 #define  SDHCI_TRNS_MULTI	0x00000020
 #define  SDHCI_TRNS_DPSEL	0x00200000
@@ -188,6 +188,17 @@
 #define SDHCI_ADMA_ADDRESS	0x58
 
 /* 60-FB reserved */
+#define SDHCI_DLL_CONTROL 	0x60
+#define DLL_CTRL_ENABLE 	0x00000001
+#define DLL_CTRL_RESET 		0x00000002
+#define DLL_CTRL_SLV_FORCE_UPD 	0x00000004
+#define DLL_CTRL_SLV_DLY_TAR 	0x00000020
+#define DLL_CTRL_SLV_UP_INT 	0x00200000
+#define DLL_CTRL_REF_UP_INT 	0x20000000
+
+#define SDHCI_DLL_STATUS 	0x64
+#define DLL_STS_SLV_LOCK 	0x00000001
+#define DLL_STS_REF_LOCK 	0x00000002
 
 /* ADMA Addr Descriptor Attribute Filed */
 enum {