diff options
| author | Robby Cai <R63905@freescale.com> | 2010-05-19 22:12:05 +0800 |
|---|---|---|
| committer | Frank Li <Frank.Li@freescale.com> | 2010-05-20 15:19:01 +0800 |
| commit | a15128d7e048f6e453dcb6ab34cbdae5d1621fc7 (patch) | |
| tree | 5702184c8bef545e9c4130e7613a4cd025f212d5 | |
| parent | d17feebffa7cf7e5cb4d7351dfab6413503b5054 (diff) | |
ENGR00123454 [MX23] FIX LCD no display issue after switch back from TVout
Due to the LCDIF clock caculation problem.
Signed-off-by: Robby Cai <R63905@freescale.com>
(cherry picked from commit a3ac3c774a71678619d34cba412a2ab535d4ab7f)
| -rw-r--r-- | arch/arm/mach-mx23/clock.c | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/arch/arm/mach-mx23/clock.c b/arch/arm/mach-mx23/clock.c index 3edc90ffe9e9..a4de6d561c87 100644 --- a/arch/arm/mach-mx23/clock.c +++ b/arch/arm/mach-mx23/clock.c @@ -482,8 +482,16 @@ out: return ret; } +/* + * We set lcdif_clk's parent as &pll_clk deliberately, although + * in IC spec lcdif_clk(CLK_PIX) is derived from ref_pix which in turn + * is derived from PLL. By doing so, users just need to set/get clock rate + * for lcdif_clk, without need to take care of ref_pix, because the clock + * driver will automatically calculate the fracdivider for HW_CLKCTRL_FRAC + * and the divider for HW_CLKCTRL_PIX conjointly. + */ static struct clk lcdif_clk = { - .parent = &ref_pix_clk, + .parent = &pll_clk, .enable = mx23_raw_enable, .disable = mx23_raw_disable, .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_PIX, @@ -1504,9 +1512,6 @@ static void print_ref_counts(void) printk(KERN_INFO "ref_emi_clk ref count: %i\n", ref_emi_clk.ref & CLK_EN_MASK); - printk(KERN_INFO "ref_pix_clk ref count: %i\n", - ref_pix_clk.ref & CLK_EN_MASK); - printk(KERN_INFO "lcdif_clk ref count: %i\n", lcdif_clk.ref & CLK_EN_MASK); |