diff options
author | Xinyu Chen <xinyu.chen@freescale.com> | 2010-03-18 09:15:21 +0800 |
---|---|---|
committer | Xinyu Chen <xinyu.chen@freescale.com> | 2010-03-19 09:32:40 +0800 |
commit | 9307cd09f9870a6982e681167d98d797f5098b3a (patch) | |
tree | e7fc515ed2c069e384f3c27eb057e98d49dc775b | |
parent | 057c8409baf6baa7e9a0cb4f674cde4b7ef9eca7 (diff) |
ENGR00121653 MX53 Add FEC support
Add FEC support for MX53 EVK
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
-rw-r--r-- | drivers/net/fec.c | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/drivers/net/fec.c b/drivers/net/fec.c index 5b63b8dc26c1..3989b481461e 100644 --- a/drivers/net/fec.c +++ b/drivers/net/fec.c @@ -1976,7 +1976,9 @@ fec_restart(struct net_device *dev, int duplex) writel(0, fep->hwp + FEC_HASH_TABLE_LOW); #endif #ifdef CONFIG_ARCH_MXC - if (cpu_is_mx25()) { + if (cpu_is_mx25() || cpu_is_mx53()) { + + unsigned int val; /* * Set up the MII gasket for RMII mode */ @@ -1987,11 +1989,18 @@ fec_restart(struct net_device *dev, int duplex) while (__raw_readl(fep->hwp + FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY) udelay(1); + val = FEC_MIIGSK_CFGR_IF_MODE_RMII; + if (cpu_is_mx53() && + fep->phy_status & (PHY_STAT_10FDX | PHY_STAT_10HDX)) /* 10Mb */ + val |= FEC_MIIGSK_CFGR_FRCONT; /* configure the gasket for RMII, 50 MHz, no loopback, no echo */ - __raw_writel(FEC_MIIGSK_CFGR_IF_MODE_RMII, fep->hwp + FEC_MIIGSK_CFGR); + __raw_writel(val, fep->hwp + FEC_MIIGSK_CFGR); /* re-enable the gasket */ __raw_writel(FEC_MIIGSK_ENR_EN, fep->hwp + FEC_MIIGSK_ENR); + while (!(__raw_readl(fep->hwp + FEC_MIIGSK_ENR) + & FEC_MIIGSK_ENR_READY)) + udelay(1); } #endif /* Set maximum receive buffer size. */ |