diff options
| author | Rob Herring <r.herring@freescale.com> | 2010-03-17 18:40:51 -0500 |
|---|---|---|
| committer | Rob Herring <r.herring@freescale.com> | 2010-03-18 08:46:37 -0500 |
| commit | 76a596db4dde5eac5fafb1604bb1f3f4a817e1d7 (patch) | |
| tree | e84a90545a4161d9d9e075cdeb73956d4335a03f | |
| parent | 7884bd3f56d749a4cff60aae129061b2e5b567e5 (diff) | |
ENGR00121700: ipu: add support for ipuv3M memory mapping
The memory map on IPUv3M is compressed into a smaller region, so
support this as revision 3 of the h/w.
Signed-off-by: Rob Herring <r.herring@freescale.com>
| -rw-r--r-- | drivers/mxc/ipu3/ipu_common.c | 5 | ||||
| -rw-r--r-- | drivers/mxc/ipu3/ipu_regs.h | 45 |
2 files changed, 29 insertions, 21 deletions
diff --git a/drivers/mxc/ipu3/ipu_common.c b/drivers/mxc/ipu3/ipu_common.c index fedd9803ee11..4b79b6a36dea 100644 --- a/drivers/mxc/ipu3/ipu_common.c +++ b/drivers/mxc/ipu3/ipu_common.c @@ -309,6 +309,11 @@ static int ipu_probe(struct platform_device *pdev) return -ENODEV; ipu_base = res->start; + if (g_ipu_hw_rev == 3) /* IPUv3M */ + ipu_base += IPUV3M_REG_BASE; + else /* IPUv3D, v3E, v3EX */ + ipu_base += IPU_REG_BASE; + ipu_cm_reg = ioremap(ipu_base + IPU_CM_REG_BASE, PAGE_SIZE); ipu_ic_reg = ioremap(ipu_base + IPU_IC_REG_BASE, PAGE_SIZE); ipu_idmac_reg = ioremap(ipu_base + IPU_IDMAC_REG_BASE, PAGE_SIZE); diff --git a/drivers/mxc/ipu3/ipu_regs.h b/drivers/mxc/ipu3/ipu_regs.h index f31e181148bb..4a5fcdc1f7e2 100644 --- a/drivers/mxc/ipu3/ipu_regs.h +++ b/drivers/mxc/ipu3/ipu_regs.h @@ -1,5 +1,5 @@ /* - * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -24,26 +24,29 @@ #define IPU_DISP0_BASE 0x00000000 #define IPU_MCU_T_DEFAULT 8 #define IPU_DISP1_BASE (IPU_MCU_T_DEFAULT << 25) -#define IPU_CM_REG_BASE 0x1E000000 -#define IPU_IDMAC_REG_BASE 0x1E008000 -#define IPU_ISP_REG_BASE 0x1E010000 -#define IPU_DP_REG_BASE 0x1E018000 -#define IPU_IC_REG_BASE 0x1E020000 -#define IPU_IRT_REG_BASE 0x1E028000 -#define IPU_CSI0_REG_BASE 0x1E030000 -#define IPU_CSI1_REG_BASE 0x1E038000 -#define IPU_DI0_REG_BASE 0x1E040000 -#define IPU_DI1_REG_BASE 0x1E048000 -#define IPU_SMFC_REG_BASE 0x1E050000 -#define IPU_DC_REG_BASE 0x1E058000 -#define IPU_DMFC_REG_BASE 0x1E060000 -#define IPU_CPMEM_REG_BASE 0x1F000000 -#define IPU_LUT_REG_BASE 0x1F020000 -#define IPU_SRM_REG_BASE 0x1F040000 -#define IPU_TPM_REG_BASE 0x1F060000 -#define IPU_DC_TMPL_REG_BASE 0x1F080000 -#define IPU_ISP_TBPR_REG_BASE 0x1F0C0000 -#define IPU_VDI_REG_BASE 0x1E068000 +#define IPU_REG_BASE 0x1E000000 +#define IPUV3M_REG_BASE 0x06000000 + +#define IPU_CM_REG_BASE 0x00000000 +#define IPU_IDMAC_REG_BASE 0x00008000 +#define IPU_ISP_REG_BASE 0x00010000 +#define IPU_DP_REG_BASE 0x00018000 +#define IPU_IC_REG_BASE 0x00020000 +#define IPU_IRT_REG_BASE 0x00028000 +#define IPU_CSI0_REG_BASE 0x00030000 +#define IPU_CSI1_REG_BASE 0x00038000 +#define IPU_DI0_REG_BASE 0x00040000 +#define IPU_DI1_REG_BASE 0x00048000 +#define IPU_SMFC_REG_BASE 0x00050000 +#define IPU_DC_REG_BASE 0x00058000 +#define IPU_DMFC_REG_BASE 0x00060000 +#define IPU_VDI_REG_BASE 0x00068000 +#define IPU_CPMEM_REG_BASE 0x01000000 +#define IPU_LUT_REG_BASE 0x01020000 +#define IPU_SRM_REG_BASE 0x01040000 +#define IPU_TPM_REG_BASE 0x01060000 +#define IPU_DC_TMPL_REG_BASE 0x01080000 +#define IPU_ISP_TBPR_REG_BASE 0x010C0000 extern u32 *ipu_cm_reg; |