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authorJie Zhou <b30303@freescale.com>2010-07-29 17:04:43 +0800
committerJie Zhou <b30303@freescale.com>2010-07-30 13:15:08 +0800
commite8ad323e64eef602ce1cfb0eb654aeac06f060c3 (patch)
tree75592c17dc7a45505676cf6787dacb5eeee628b2
parent9c2baf924ee738127f3d1b06d5a2eda0c3e8ce1c (diff)
ENGR00125729-1 MX5x MSL: set gpu resources correctly
MX50 has no 3D interrupt, 3D register space, and gmem Signed-off-by: Jie Zhou <b30303@freescale.com>
-rw-r--r--arch/arm/mach-mx5/devices.c14
1 files changed, 12 insertions, 2 deletions
diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c
index d9a425880f26..5ef1e9691aa8 100644
--- a/arch/arm/mach-mx5/devices.c
+++ b/arch/arm/mach-mx5/devices.c
@@ -1593,10 +1593,20 @@ int __init mxc_init_devices(void)
usbh2_resources[0].end -= MX53_OFFSET;
mxc_gpu_resources[2].start = MX53_GPU2D_BASE_ADDR;
mxc_gpu_resources[2].end = MX53_GPU2D_BASE_ADDR + SZ_4K - 1;
- mxc_gpu_resources[4].start = MX53_GPU_GMEM_BASE_ADDR;
- mxc_gpu_resources[4].end = MX53_GPU_GMEM_BASE_ADDR + SZ_256K - 1;
mxc_gpu2d_resources[0].start = MX53_GPU2D_BASE_ADDR;
mxc_gpu2d_resources[0].end = MX53_GPU2D_BASE_ADDR + SZ_4K - 1;
+ if (cpu_is_mx53()) {
+ mxc_gpu_resources[4].start = MX53_GPU_GMEM_BASE_ADDR;
+ mxc_gpu_resources[4].end = MX53_GPU_GMEM_BASE_ADDR
+ + SZ_256K - 1;
+ } else {
+ mxc_gpu_resources[1].start = 0;
+ mxc_gpu_resources[1].end = 0;
+ mxc_gpu_resources[3].start = 0;
+ mxc_gpu_resources[3].end = 0;
+ mxc_gpu_resources[4].start = 0;
+ mxc_gpu_resources[4].end = 0;
+ }
ipu_resources[0].start = MX53_IPU_CTRL_BASE_ADDR;
ipu_resources[0].end = MX53_IPU_CTRL_BASE_ADDR + SZ_128M - 1;
mlb_resources[0].start -= MX53_OFFSET;