ENGR00125578-1 mx50 clock: add WAIT macro

Use WAIT for wait loop.

Signed-off-by: Richard Zhao <richard.zhao@freescale.com>

1 files changed, 30 insertions, 48 deletions

diff --git a/arch/arm/mach-mx5/clock_mx50.c b/arch/arm/mach-mx5/clock_mx50.c
index a47f461bc2fc..7efe52adcb24 100644
--- a/arch/arm/mach-mx5/clock_mx50.c
+++ b/arch/arm/mach-mx5/clock_mx50.c
@@ -67,6 +67,19 @@ extern int lp_high_freq;
 extern int lp_med_freq;
 
 #define SPIN_DELAY	1000000 /* in nanoseconds */
+#define WAIT(exp, timeout) \
+({ \
+	struct timespec nstimeofday; \
+	struct timespec curtime; \
+	int result = 1; \
+	getnstimeofday(&nstimeofday); \
+	while (!(exp)) { \
+		getnstimeofday(&curtime); \
+		if ((curtime.tv_nsec - nstimeofday.tv_nsec) > (timeout)) \
+			result = 0; \
+	} \
+	result; \
+})
 
 extern int mxc_jtag_enabled;
 extern int uart_at_24;
@@ -502,8 +515,6 @@ static int _clk_pll_set_rate(struct clk *clk, unsigned long rate)
 {
 	u32 reg, reg1;
 	void __iomem *pllbase;
-	struct timespec nstimeofday;
-	struct timespec curtime;
 
 	long mfi, pdf, mfn, mfd = 999999;
 	s64 temp64;
@@ -551,13 +562,9 @@ static int _clk_pll_set_rate(struct clk *clk, unsigned long rate)
 			__raw_writel(reg1, pllbase + MXC_PLL_DP_CTL);
 		}
 		/* Wait for lock */
-		getnstimeofday(&nstimeofday);
-		while (!(__raw_readl(pllbase + MXC_PLL_DP_CTL)
-					& MXC_PLL_DP_CTL_LRF)) {
-			getnstimeofday(&curtime);
-			if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY)
-				panic("pll_set_rate: pll relock failed\n");
-		}
+		if (!WAIT(__raw_readl(pllbase + MXC_PLL_DP_CTL)
+			  & MXC_PLL_DP_CTL_LRF, SPIN_DELAY))
+			panic("pll_set_rate: pll relock failed\n");
 	}
 	clk->rate = rate;
 	return 0;
@@ -567,20 +574,15 @@ static int _clk_pll_enable(struct clk *clk)
 {
 	u32 reg;
 	void __iomem *pllbase;
-	struct timespec nstimeofday;
-	struct timespec curtime;
 
 	pllbase = _get_pll_base(clk);
 	reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN;
 	__raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
 
 	/* Wait for lock */
-	getnstimeofday(&nstimeofday);
-	while (!(__raw_readl(pllbase + MXC_PLL_DP_CTL) & MXC_PLL_DP_CTL_LRF)) {
-		getnstimeofday(&curtime);
-		if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY)
-			panic("pll relock failed\n");
-	}
+	if (!WAIT(__raw_readl(pllbase + MXC_PLL_DP_CTL) & MXC_PLL_DP_CTL_LRF,
+				SPIN_DELAY))
+		panic("pll relock failed\n");
 	return 0;
 }
 
@@ -824,8 +826,6 @@ static void _clk_axi_a_recalc(struct clk *clk)
 static int _clk_axi_a_set_rate(struct clk *clk, unsigned long rate)
 {
 	u32 reg, div;
-	struct timespec nstimeofday;
-	struct timespec curtime;
 
 	div = clk->parent->rate / rate;
 	if (div == 0)
@@ -838,12 +838,9 @@ static int _clk_axi_a_set_rate(struct clk *clk, unsigned long rate)
 	reg |= (div - 1) << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET;
 	__raw_writel(reg, MXC_CCM_CBCDR);
 
-	getnstimeofday(&nstimeofday);
-	while (__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_AXI_A_PODF_BUSY) {
-		getnstimeofday(&curtime);
-		if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY)
-			panic("pll _clk_axi_a_set_rate failed\n");
-	}
+	if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
+	     & MXC_CCM_CDHIPR_AXI_A_PODF_BUSY), SPIN_DELAY))
+		panic("pll _clk_axi_a_set_rate failed\n");
 	clk->rate = rate;
 
 	return 0;
@@ -885,8 +882,6 @@ static void _clk_axi_b_recalc(struct clk *clk)
 static int _clk_axi_b_set_rate(struct clk *clk, unsigned long rate)
 {
 	u32 reg, div;
-	struct timespec nstimeofday;
-	struct timespec curtime;
 
 	div = clk->parent->rate / rate;
 	if (div == 0)
@@ -899,12 +894,9 @@ static int _clk_axi_b_set_rate(struct clk *clk, unsigned long rate)
 	reg |= (div - 1) << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET;
 	__raw_writel(reg, MXC_CCM_CBCDR);
 
-	getnstimeofday(&nstimeofday);
-	while (__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_AXI_B_PODF_BUSY) {
-		getnstimeofday(&curtime);
-		if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY)
-			panic("_clk_axi_b_set_rate failed\n");
-	}
+	if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
+	     & MXC_CCM_CDHIPR_AXI_B_PODF_BUSY), SPIN_DELAY))
+		panic("_clk_axi_b_set_rate failed\n");
 
 	clk->rate = rate;
 
@@ -948,8 +940,6 @@ static void _clk_ahb_recalc(struct clk *clk)
 static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate)
 {
 	u32 reg, div;
-	struct timespec nstimeofday;
-	struct timespec curtime;
 
 	div = clk->parent->rate / rate;
 	if (div == 0)
@@ -962,12 +952,9 @@ static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate)
 	reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET;
 	__raw_writel(reg, MXC_CCM_CBCDR);
 
-	getnstimeofday(&nstimeofday);
-	while (__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_AHB_PODF_BUSY) {
-		getnstimeofday(&curtime);
-		if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY)
+	if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_AHB_PODF_BUSY),
+				SPIN_DELAY))
 			panic("_clk_ahb_set_rate failed\n");
-	}
 	clk->rate = rate;
 
 	return 0;
@@ -1062,8 +1049,6 @@ static void _clk_weim_recalc(struct clk *clk)
 static int _clk_weim_set_rate(struct clk *clk, unsigned long rate)
 {
 	u32 reg, div;
-	struct timespec nstimeofday;
-	struct timespec curtime;
 
 	div = clk->parent->rate / rate;
 	if (div == 0)
@@ -1074,12 +1059,9 @@ static int _clk_weim_set_rate(struct clk *clk, unsigned long rate)
 	reg &= ~MXC_CCM_CBCDR_EMI_PODF_MASK;
 	reg |= (div - 1) << MXC_CCM_CBCDR_EMI_PODF_OFFSET;
 	__raw_writel(reg, MXC_CCM_CBCDR);
-	getnstimeofday(&nstimeofday);
-	while (__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_EMI_PODF_BUSY) {
-		getnstimeofday(&curtime);
-		if ((curtime.tv_nsec - nstimeofday.tv_nsec) > SPIN_DELAY)
-			panic("_clk_emi_slow_set_rate failed\n");
-	}
+	if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_EMI_PODF_BUSY),
+		  SPIN_DELAY))
+		panic("_clk_emi_slow_set_rate failed\n");
 	clk->rate = rate;
 
 	return 0;