ENGR00125323-1: MX50: Change MXC iomux to use iomux-v3

To better align Freescale's BSP to kernel.org, it is
better to use iomux-v3 instead of mxc_iomux.

Change mx50 iomux to use iomux-v3.

- Creates iomux-mx50.h to defines IOMUX pins for MX50 HW
- Moves pin structure and functions that were in
  mx50_arm2_gpio.c into mx50_arm2.c and deletes
  mx50_arm2_gpio.c.

Signed-off-by: Dinh Nguyen <Dinh.Nguyen@freescale.com>

10 files changed, 852 insertions, 1087 deletions

diff --git a/arch/arm/configs/imx5_defconfig b/arch/arm/configs/imx5_defconfig
index c4496f9f591e..501c442c282d 100644
--- a/arch/arm/configs/imx5_defconfig
+++ b/arch/arm/configs/imx5_defconfig
@@ -204,6 +204,7 @@ CONFIG_MACH_MX51_3DS=y
 CONFIG_MACH_MX51_BABBAGE=y
 CONFIG_MACH_MX53_EVK=y
 CONFIG_MACH_MX50_ARM2=y
+CONFIG_ARCH_MXC_IOMUX_V3=y
 
 #
 # MX5x Options:
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index 341b4475872d..2795773086e7 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -2,6 +2,7 @@ if ARCH_MX5
 
 config ARCH_MX51
 	bool
+	select ARCH_MXC_IOMUX_V3
 
 config ARCH_MX53
 	bool
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
index 453b96cbe5ed..edac948cb9c0 100644
--- a/arch/arm/mach-mx5/Makefile
+++ b/arch/arm/mach-mx5/Makefile
@@ -15,4 +15,4 @@ obj-$(CONFIG_ARCH_MX50) += clock_mx50.o mx50_suspend.o
 obj-$(CONFIG_MACH_MX51_3DS) += mx51_3stack.o mx51_3stack_gpio.o mx51_3stack_pmic_mc13892.o
 obj-$(CONFIG_MACH_MX51_BABBAGE) += mx51_babbage.o mx51_babbage_gpio.o mx51_babbage_pmic_mc13892.o
 obj-$(CONFIG_MACH_MX53_EVK) += mx53_evk.o mx53_evk_gpio.o mx53_evk_pmic_mc13892.o
-obj-$(CONFIG_MACH_MX50_ARM2) += mx50_arm2.o mx50_arm2_gpio.o mx50_arm2_pmic_mc13892.o
+obj-$(CONFIG_MACH_MX50_ARM2) += mx50_arm2.o mx50_arm2_pmic_mc13892.o
diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c
index 226083e1f703..04881ee530d7 100644
--- a/arch/arm/mach-mx5/mm.c
+++ b/arch/arm/mach-mx5/mm.c
@@ -16,6 +16,7 @@
 #include <mach/hardware.h>
 #include <asm/pgtable.h>
 #include <asm/mach/map.h>
+#include <mach/iomux-v3.h>
 
 /*!
  * @file mach-mx51/mm.c
@@ -55,6 +56,7 @@ void __init mx5_map_io(void)
 {
 	int i;
 
+	mxc_iomux_v3_init(IO_ADDRESS(IOMUXC_BASE_ADDR));
 	/* Fixup the mappings for MX53 */
 	if (cpu_is_mx53() || cpu_is_mx50()) {
 		for (i = 0; i < ARRAY_SIZE(mx5_io_desc); i++)
diff --git a/arch/arm/mach-mx5/mx50_arm2.c b/arch/arm/mach-mx5/mx50_arm2.c
index 82b67b3faa12..d9e37be9aa5e 100644
--- a/arch/arm/mach-mx5/mx50_arm2.c
+++ b/arch/arm/mach-mx5/mx50_arm2.c
@@ -56,17 +56,174 @@
 #include <mach/gpio.h>
 #include <mach/mmc.h>
 #include <mach/mxc_dvfs.h>
-#include "iomux.h"
-#include "mx50_pins.h"
+#include <mach/iomux-mx50.h>
+
 #include "devices.h"
 #include "usb.h"
 
-extern void __init mx50_arm2_io_init(void);
+#define SD1_WP	(3*32 + 19)	/*GPIO_4_19 */
+#define SD1_CD	(0*32 + 27)	/*GPIO_1_27 */
+#define SD2_WP	(4*32 + 16)	/*GPIO_5_16 */
+#define SD2_CD	(4*32 + 17) /*GPIO_5_17 */
+#define SD3_WP	(4*32 + 28) /*GPIO_5_28 */
+#define SD3_CD	(3*32 + 4) /*GPIO_4_4 */
+#define HP_DETECT	(3*32 + 15)	/*GPIO_4_15 */
+#define PWR_INT		(3*32 + 18)	/*GPIO_4_18 */
+#define EPDC_PMIC_WAKE		(5*32 + 16)	/*GPIO_6_16 */
+#define EPDC_PMIC_INT		(5*32 + 17)	/*GPIO_6_17 */
+#define EPDC_VCOM	(3*32 + 21)	/*GPIO_4_21 */
+#define EPDC_PWRSTAT	(2*32 + 28)	/*GPIO_3_28 */
+#define EPDC_ELCDIF_BACKLIGHT	(1*32 + 18)	/*GPIO_2_18 */
+#define CSPI_CS1	(3*32 + 13)	/*GPIO_4_13 */
+#define CSPI_CS2	(3*32 + 11) /*GPIO_4_11*/
+
 extern int __init mx50_arm2_init_mc13892(void);
 extern struct cpu_wp *(*get_cpu_wp)(int *wp);
 extern void (*set_num_cpu_wp)(int num);
 static int num_cpu_wp = 3;
 
+static struct pad_desc  mx50_armadillo2[] = {
+	/* SD1 */
+	MX50_PAD_ECSPI2_SS0__GPIO_4_19,
+	MX50_PAD_EIM_CRE__GPIO_1_27,
+	MX50_PAD_SD1_CMD__SD1_CMD,
+
+	MX50_PAD_SD1_CLK__SD1_CLK,
+	MX50_PAD_SD1_D0__SD1_D0,
+	MX50_PAD_SD1_D1__SD1_D1,
+	MX50_PAD_SD1_D2__SD1_D2,
+	MX50_PAD_SD1_D3__SD1_D3,
+
+	/* SD2 */
+	MX50_PAD_SD2_CD__GPIO_5_17,
+	MX50_PAD_SD2_WP__GPIO_5_16,
+	MX50_PAD_SD2_CMD__SD2_CMD,
+	MX50_PAD_SD2_CLK__SD2_CLK,
+	MX50_PAD_SD2_D0__SD2_D0,
+	MX50_PAD_SD2_D1__SD2_D1,
+	MX50_PAD_SD2_D2__SD2_D2,
+	MX50_PAD_SD2_D3__SD2_D3,
+	MX50_PAD_SD2_D4__SD2_D4,
+	MX50_PAD_SD2_D5__SD2_D5,
+	MX50_PAD_SD2_D6__SD2_D6,
+	MX50_PAD_SD2_D7__SD2_D7,
+
+	/* SD3 */
+	MX50_PAD_SD3_WP__GPIO_5_28,
+	MX50_PAD_KEY_COL2__GPIO_4_4,
+	MX50_PAD_SD3_CMD__SD3_CMD,
+	MX50_PAD_SD3_CLK__SD3_CLK,
+	MX50_PAD_SD3_D0__SD3_D0,
+	MX50_PAD_SD3_D1__SD3_D1,
+	MX50_PAD_SD3_D2__SD3_D2,
+	MX50_PAD_SD3_D3__SD3_D3,
+	MX50_PAD_SD3_D4__SD3_D4,
+	MX50_PAD_SD3_D5__SD3_D5,
+	MX50_PAD_SD3_D6__SD3_D6,
+	MX50_PAD_SD3_D7__SD3_D7,
+
+	MX50_PAD_SSI_RXD__SSI_RXD,
+	MX50_PAD_SSI_TXD__SSI_TXD,
+	MX50_PAD_SSI_TXC__SSI_TXC,
+	MX50_PAD_SSI_TXFS__SSI_TXFS,
+
+	/* LINE1_DETECT (headphone detect) */
+	MX50_PAD_ECSPI1_SS0__GPIO_4_15,
+
+	/* PWR_INT */
+	MX50_PAD_ECSPI2_MISO__GPIO_4_18,
+
+	/* UART pad setting */
+	MX50_PAD_UART1_TXD__UART1_TXD,
+	MX50_PAD_UART1_RXD__UART1_RXD,
+	MX50_PAD_UART1_CTS__UART1_CTS,
+	MX50_PAD_UART1_RTS__UART1_RTS,
+	MX50_PAD_UART2_TXD__UART2_TXD,
+	MX50_PAD_UART2_RXD__UART2_RXD,
+	MX50_PAD_UART2_CTS__UART2_CTS,
+	MX50_PAD_UART2_RTS__UART2_RTS,
+
+	MX50_PAD_I2C1_SCL__I2C1_SCL,
+	MX50_PAD_I2C1_SDA__I2C1_SDA,
+	MX50_PAD_I2C2_SCL__I2C2_SCL,
+	MX50_PAD_I2C2_SDA__I2C2_SDA,
+	MX50_PAD_I2C3_SCL__I2C3_SCL,
+	MX50_PAD_I2C3_SDA__I2C3_SDA,
+
+	/* EPDC pins */
+	MX50_PAD_EPDC_D0__EPDC_D0,
+	MX50_PAD_EPDC_D1__EPDC_D1,
+	MX50_PAD_EPDC_D2__EPDC_D2,
+	MX50_PAD_EPDC_D3__EPDC_D3,
+	MX50_PAD_EPDC_D4__EPDC_D4,
+	MX50_PAD_EPDC_D5__EPDC_D5,
+	MX50_PAD_EPDC_D6__EPDC_D6,
+	MX50_PAD_EPDC_D7__EPDC_D7,
+	MX50_PAD_EPDC_GDCLK__EPDC_GDCLK,
+	MX50_PAD_EPDC_GDSP__EPDC_GDSP,
+	MX50_PAD_EPDC_GDOE__EPDC_GDOE	,
+	MX50_PAD_EPDC_GDRL__EPDC_GDRL,
+	MX50_PAD_EPDC_SDCLK__EPDC_SDCLK,
+	MX50_PAD_EPDC_SDOE__EPDC_SDOE,
+	MX50_PAD_EPDC_SDLE__EPDC_SDLE,
+	MX50_PAD_EPDC_SDSHR__EPDC_SDSHR,
+	MX50_PAD_EPDC_BDR0__EPDC_BDR0,
+	MX50_PAD_EPDC_SDCE0__EPDC_SDCE0,
+	MX50_PAD_EPDC_SDCE1__EPDC_SDCE1,
+	MX50_PAD_EPDC_SDCE2__EPDC_SDCE2,
+
+	MX50_PAD_EPDC_PWRSTAT__GPIO_3_28,
+	MX50_PAD_EPDC_VCOM0__GPIO_4_21,
+
+	MX50_PAD_DISP_D8__DISP_D8,
+	MX50_PAD_DISP_D9__DISP_D9,
+	MX50_PAD_DISP_D10__DISP_D10,
+	MX50_PAD_DISP_D11__DISP_D11,
+	MX50_PAD_DISP_D12__DISP_D12,
+	MX50_PAD_DISP_D13__DISP_D13,
+	MX50_PAD_DISP_D14__DISP_D14,
+	MX50_PAD_DISP_D15__DISP_D15,
+	MX50_PAD_DISP_RS__ELCDIF_VSYNC,
+
+	/* ELCDIF contrast */
+	MX50_PAD_DISP_BUSY__GPIO_2_18,
+
+	MX50_PAD_DISP_CS__ELCDIF_HSYNC,
+	MX50_PAD_DISP_RD__ELCDIF_EN,
+	MX50_PAD_DISP_WR__ELCDIF_PIXCLK,
+
+	/* EPD PMIC WAKEUP */
+	MX50_PAD_UART4_TXD__GPIO_6_16,
+
+	/* EPD PMIC intr */
+	MX50_PAD_UART4_RXD__GPIO_6_17,
+
+	MX50_PAD_EPITO__USBH1_PWR,
+	/* Need to comment below line if
+	 * one needs to debug owire.
+	 */
+	MX50_PAD_OWIRE__USBH1_OC,
+	MX50_PAD_PWM2__USBOTG_PWR,
+	MX50_PAD_PWM1__USBOTG_OC,
+
+	MX50_PAD_SSI_RXC__FEC_MDIO,
+	MX50_PAD_SSI_RXC__FEC_MDIO,
+	MX50_PAD_DISP_D0__FEC_TXCLK,
+	MX50_PAD_DISP_D1__FEC_RX_ER,
+	MX50_PAD_DISP_D2__FEC_RX_DV,
+	MX50_PAD_DISP_D3__FEC_RXD1,
+	MX50_PAD_DISP_D4__FEC_RXD0,
+	MX50_PAD_DISP_D5__FEC_TX_EN,
+	MX50_PAD_DISP_D6__FEC_TXD1,
+	MX50_PAD_DISP_D7__FEC_TXD0,
+	MX50_PAD_SSI_RXFS__FEC_MDC,
+
+	MX50_PAD_CSPI_SS0__CSPI_SS0,
+	MX50_PAD_ECSPI1_MOSI__CSPI_SS1,
+	MX50_PAD_CSPI_MOSI__CSPI_MOSI,
+	MX50_PAD_CSPI_MISO__CSPI_MISO,
+};
+
 /* working point(wp): 0 - 800MHz; 1 - 166.25MHz; */
 static struct cpu_wp cpu_wp_auto[] = {
 	{
@@ -118,10 +275,80 @@ static struct fec_platform_data fec_data = {
 	.phy = PHY_INTERFACE_MODE_RMII,
 };
 
-extern void mx50_arm2_gpio_spi_chipselect_active(int cspi_mode, int status,
-						    int chipselect);
-extern void mx50_arm2_gpio_spi_chipselect_inactive(int cspi_mode, int status,
-						      int chipselect);
+/* workaround for cspi chipselect pin may not keep correct level when idle */
+static void mx50_arm2_gpio_spi_chipselect_active(int cspi_mode, int status,
+					     int chipselect)
+{
+	switch (cspi_mode) {
+	case 1:
+		break;
+	case 2:
+		break;
+	case 3:
+		switch (chipselect) {
+		case 0x1:
+			{
+			struct pad_desc cspi_ss0 = MX50_PAD_CSPI_SS0__CSPI_SS0;
+			struct pad_desc cspi_cs1 = MX50_PAD_ECSPI1_MOSI__GPIO_4_13;
+
+			/* pull up/down deassert it */
+			mxc_iomux_v3_setup_pad(&cspi_ss0);
+			mxc_iomux_v3_setup_pad(&cspi_cs1);
+
+			gpio_request(CSPI_CS1, "cspi-cs1");
+			gpio_direction_input(CSPI_CS1);
+			}
+			break;
+		case 0x2:
+			{
+			struct pad_desc cspi_ss1 = MX50_PAD_ECSPI1_MOSI__CSPI_SS1;
+			struct pad_desc cspi_ss0 = MX50_PAD_CSPI_SS0__GPIO_4_11;
+
+			/*disable other ss */
+			mxc_iomux_v3_setup_pad(&cspi_ss1);
+			mxc_iomux_v3_setup_pad(&cspi_ss0);
+
+			/* pull up/down deassert it */
+			gpio_request(CSPI_CS2, "cspi-cs2");
+			gpio_direction_input(CSPI_CS2);
+			}
+			break;
+		default:
+			break;
+		}
+		break;
+
+	default:
+		break;
+	}
+}
+
+static void mx50_arm2_gpio_spi_chipselect_inactive(int cspi_mode, int status,
+					       int chipselect)
+{
+	switch (cspi_mode) {
+	case 1:
+		break;
+	case 2:
+		break;
+	case 3:
+		switch (chipselect) {
+		case 0x1:
+			gpio_free(CSPI_CS1);
+			break;
+		case 0x2:
+			gpio_free(CSPI_CS2);
+			break;
+		default:
+			break;
+		}
+		break;
+	default:
+		break;
+	}
+
+}
+
 static struct mxc_spi_master mxcspi1_data = {
 	.maxchipselect = 4,
 	.spi_version = 23,
@@ -209,10 +436,10 @@ static struct max17135_platform_data max17135_pdata __initdata = {
 	.vpos_pwrdn = 2,
 	.gvee_pwrdn = 1,
 	.vneg_pwrdn = 1,
-	.gpio_pmic_pwrgood = IOMUX_TO_GPIO(MX50_PIN_EPDC_PWRSTAT),
-	.gpio_pmic_vcom_ctrl = IOMUX_TO_GPIO(MX50_PIN_EPDC_VCOM0),
-	.gpio_pmic_wakeup = IOMUX_TO_GPIO(MX50_PIN_UART4_TXD),
-	.gpio_pmic_intr = IOMUX_TO_GPIO(MX50_PIN_UART4_RXD),
+	.gpio_pmic_pwrgood = EPDC_PWRSTAT,
+	.gpio_pmic_vcom_ctrl = EPDC_VCOM,
+	.gpio_pmic_wakeup = EPDC_PMIC_WAKE,
+	.gpio_pmic_intr = EPDC_PMIC_INT,
 	.regulator_init = max17135_init_data,
 };
 
@@ -272,24 +499,24 @@ static int sdhc_write_protect(struct device *dev)
 	unsigned short rc = 0;
 
 	if (to_platform_device(dev)->id == 0)
-		rc = gpio_get_value(IOMUX_TO_GPIO(MX50_PIN_ECSPI2_SS0));
+		rc = gpio_get_value(SD1_WP);
 	else if (to_platform_device(dev)->id == 1)
-		rc = gpio_get_value(IOMUX_TO_GPIO(MX50_PIN_SD2_WP));
+		rc = gpio_get_value(SD2_WP);
 	else if (to_platform_device(dev)->id == 2)
-		rc = gpio_get_value(IOMUX_TO_GPIO(MX50_PIN_SD3_WP));
+		rc = gpio_get_value(SD3_WP);
 
 	return rc;
 }
 
 static unsigned int sdhc_get_card_det_status(struct device *dev)
 {
-	int ret;
+	int ret = 0;
 	if (to_platform_device(dev)->id == 0)
-		ret = gpio_get_value(IOMUX_TO_GPIO(MX50_PIN_EIM_CRE));
+		ret = gpio_get_value(SD1_CD);
 	else if (to_platform_device(dev)->id == 1)
-		ret = gpio_get_value(IOMUX_TO_GPIO(MX50_PIN_SD2_CD));
+		ret = gpio_get_value(SD2_CD);
 	else if (to_platform_device(dev)->id == 2)
-		ret = gpio_get_value(IOMUX_TO_GPIO(MX50_PIN_KEY_COL2));
+		ret = gpio_get_value(SD3_CD);
 
 	return ret;
 }
@@ -339,14 +566,14 @@ static int mxc_sgtl5000_amp_enable(int enable)
 
 static int headphone_det_status(void)
 {
-	return (gpio_get_value(IOMUX_TO_GPIO(MX50_PIN_ECSPI1_SS0)) != 0);
+	return (gpio_get_value(HP_DETECT) != 0);
 }
 
 static struct mxc_audio_platform_data sgtl5000_data = {
 	.ssi_num = 1,
 	.src_port = 2,
 	.ext_port = 3,
-	.hp_irq = IOMUX_TO_IRQ(MX50_PIN_ECSPI1_SS0),
+	.hp_irq = IOMUX_TO_IRQ_V3(HP_DETECT),
 	.hp_status = headphone_det_status,
 	.amp_enable = mxc_sgtl5000_amp_enable,
 	.sysclk = 12288000,
@@ -356,64 +583,21 @@ static struct platform_device mxc_sgtl5000_device = {
 	.name = "imx-3stack-sgtl5000",
 };
 
+static struct pad_desc armadillo2_wvga_pads[] = {
+	MX50_PAD_DISP_D0__DISP_D0,
+	MX50_PAD_DISP_D1__DISP_D1,
+	MX50_PAD_DISP_D2__DISP_D2,
+	MX50_PAD_DISP_D3__DISP_D3,
+	MX50_PAD_DISP_D4__DISP_D4,
+	MX50_PAD_DISP_D5__DISP_D5,
+	MX50_PAD_DISP_D6__DISP_D6,
+	MX50_PAD_DISP_D7__DISP_D7,
+};
+
 static void wvga_reset(void)
 {
-	/* ELCDIF D0 */
-	mxc_free_iomux(MX50_PIN_DISP_D0, IOMUX_CONFIG_ALT2);
-	mxc_request_iomux(MX50_PIN_DISP_D0, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX50_PIN_DISP_D0, PAD_CTL_PKE_ENABLE |
-			  PAD_CTL_PUE_KEEPER |
-			  PAD_CTL_ODE_OPENDRAIN_NONE |
-			  PAD_CTL_DRV_HIGH);
-	/* ELCDIF D1 */
-	mxc_free_iomux(MX50_PIN_DISP_D1, IOMUX_CONFIG_ALT2);
-	mxc_request_iomux(MX50_PIN_DISP_D1, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX50_PIN_DISP_D1, PAD_CTL_PKE_ENABLE |
-			  PAD_CTL_PUE_KEEPER |
-			  PAD_CTL_ODE_OPENDRAIN_NONE |
-			  PAD_CTL_DRV_HIGH);
-	/* ELCDIF D2 */
-	mxc_free_iomux(MX50_PIN_DISP_D2, IOMUX_CONFIG_ALT2);
-	mxc_request_iomux(MX50_PIN_DISP_D2, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX50_PIN_DISP_D2, PAD_CTL_PKE_ENABLE |
-			  PAD_CTL_PUE_KEEPER |
-			  PAD_CTL_ODE_OPENDRAIN_NONE |
-			  PAD_CTL_DRV_HIGH);
-	/* ELCDIF D3 */
-	mxc_free_iomux(MX50_PIN_DISP_D3, IOMUX_CONFIG_ALT2);
-	mxc_request_iomux(MX50_PIN_DISP_D3, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX50_PIN_DISP_D3, PAD_CTL_PKE_ENABLE |
-			  PAD_CTL_PUE_KEEPER |
-			  PAD_CTL_ODE_OPENDRAIN_NONE |
-			  PAD_CTL_DRV_HIGH);
-	/* ELCDIF D4 */
-	mxc_free_iomux(MX50_PIN_DISP_D4, IOMUX_CONFIG_ALT2);
-	mxc_request_iomux(MX50_PIN_DISP_D4, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX50_PIN_DISP_D4, PAD_CTL_PKE_ENABLE |
-			  PAD_CTL_PUE_KEEPER |
-			  PAD_CTL_ODE_OPENDRAIN_NONE |
-			  PAD_CTL_DRV_HIGH);
-	/* ELCDIF D5 */
-	mxc_free_iomux(MX50_PIN_DISP_D5, IOMUX_CONFIG_ALT2);
-	mxc_request_iomux(MX50_PIN_DISP_D5, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX50_PIN_DISP_D5, PAD_CTL_PKE_ENABLE |
-			  PAD_CTL_PUE_KEEPER |
-			  PAD_CTL_ODE_OPENDRAIN_NONE |
-			  PAD_CTL_DRV_HIGH);
-	/* ELCDIF D6 */
-	mxc_free_iomux(MX50_PIN_DISP_D6, IOMUX_CONFIG_ALT2);
-	mxc_request_iomux(MX50_PIN_DISP_D6, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX50_PIN_DISP_D6, PAD_CTL_PKE_ENABLE |
-			  PAD_CTL_PUE_KEEPER |
-			  PAD_CTL_ODE_OPENDRAIN_NONE |
-			  PAD_CTL_DRV_HIGH);
-	/* ELCDIF D7 */
-	mxc_free_iomux(MX50_PIN_DISP_D7, IOMUX_CONFIG_ALT2);
-	mxc_request_iomux(MX50_PIN_DISP_D7, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX50_PIN_DISP_D7, PAD_CTL_PKE_ENABLE |
-			  PAD_CTL_PUE_KEEPER |
-			  PAD_CTL_ODE_OPENDRAIN_NONE |
-			  PAD_CTL_DRV_HIGH);
+	mxc_iomux_v3_setup_multiple_pads(armadillo2_wvga_pads, \
+				ARRAY_SIZE(armadillo2_wvga_pads));
 	return;
 }
 
@@ -446,6 +630,15 @@ static struct mxc_fb_platform_data fb_data[] = {
 	 },
 };
 
+static int __initdata enable_w1 = { 0 };
+static int __init w1_setup(char *__unused)
+{
+	enable_w1 = 1;
+	return cpu_is_mx50();
+}
+
+__setup("w1", w1_setup);
+
 /*!
  * Board specific fixup function. It is called by \b setup_arch() in
  * setup.c file very early on during kernel starts. It allows the user to
@@ -466,18 +659,69 @@ static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags,
 	set_num_cpu_wp = mx50_arm2_set_num_cpu_wp;
 }
 
+static void __init mx50_arm2_io_init(void)
+{
+	mxc_iomux_v3_setup_multiple_pads(mx50_armadillo2, \
+			ARRAY_SIZE(mx50_armadillo2));
+
+	gpio_request(SD1_WP, "sdhc1-wp");
+	gpio_direction_input(SD1_WP);
+
+	gpio_request(SD1_CD, "sdhc1-cd");
+	gpio_direction_input(SD1_CD);
+
+	gpio_request(SD2_WP, "sdhc2-wp");
+	gpio_direction_input(SD2_WP);
+
+	gpio_request(SD2_CD, "sdhc2-cd");
+	gpio_direction_input(SD2_CD);
+
+	gpio_request(SD3_WP, "sdhc3-wp");
+	gpio_direction_input(SD3_WP);
+
+	gpio_request(SD3_CD, "sdhc3-cd");
+	gpio_direction_input(SD3_CD);
+
+	gpio_request(HP_DETECT, "hp-det");
+	gpio_direction_input(HP_DETECT);
+
+	gpio_request(PWR_INT, "pwr-int");
+	gpio_direction_input(PWR_INT);
+
+	gpio_request(EPDC_PMIC_WAKE, "epdc-pmic-wake");
+	gpio_direction_output(EPDC_PMIC_WAKE, 0);
+
+	gpio_request(EPDC_VCOM, "epdc-vcom");
+	gpio_direction_output(EPDC_VCOM, 0);
+
+	gpio_request(EPDC_PMIC_INT, "epdc-pmic-int");
+	gpio_direction_input(EPDC_PMIC_INT);
+
+	gpio_request(EPDC_PWRSTAT, "epdc-pwrstat");
+	gpio_direction_input(EPDC_PWRSTAT);
+
+	/* ELCDIF backlight */
+	gpio_request(EPDC_ELCDIF_BACKLIGHT, "elcdif-backlight");
+	gpio_direction_output(EPDC_ELCDIF_BACKLIGHT, 1);
+
+	if (enable_w1) {
+		struct pad_desc one_wire = MX50_PAD_OWIRE__OWIRE;
+		mxc_iomux_v3_setup_pad(&one_wire);
+	}
+}
+
 /*!
  * Board specific initialization.
  */
 static void __init mxc_board_init(void)
 {
 	/* SD card detect irqs */
-	mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ(MX50_PIN_EIM_CRE);
-	mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ(MX50_PIN_EIM_CRE);
-	mxcsdhc2_device.resource[2].start = IOMUX_TO_IRQ(MX50_PIN_SD2_CD);
-	mxcsdhc2_device.resource[2].end = IOMUX_TO_IRQ(MX50_PIN_SD2_CD);
-	mxcsdhc3_device.resource[2].start = IOMUX_TO_IRQ(MX50_PIN_KEY_COL2);
-	mxcsdhc3_device.resource[2].end = IOMUX_TO_IRQ(MX50_PIN_KEY_COL2);
+	mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ_V3(SD1_CD);
+	mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ_V3(SD1_CD);
+	mxcsdhc2_device.resource[2].start = IOMUX_TO_IRQ_V3(SD2_CD);
+	mxcsdhc2_device.resource[2].end = IOMUX_TO_IRQ_V3(SD2_CD);
+	mxcsdhc3_device.resource[2].start = IOMUX_TO_IRQ_V3(SD3_CD);
+	mxcsdhc3_device.resource[2].end = IOMUX_TO_IRQ_V3(SD3_CD);
 
 	mxc_cpu_common_init();
 	mxc_register_gpios();
diff --git a/arch/arm/mach-mx5/mx50_arm2_gpio.c b/arch/arm/mach-mx5/mx50_arm2_gpio.c
deleted file mode 100644
index 8b37784ef9b5..000000000000
--- a/arch/arm/mach-mx5/mx50_arm2_gpio.c
+++ /dev/null
@@ -1,658 +0,0 @@
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#include <linux/errno.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <mach/gpio.h>
-
-#include "iomux.h"
-#include "mx50_pins.h"
-
-/*!
- * @file mach-mx5/mx50_arm2_gpio.c
- *
- * @brief This file contains all the GPIO setup functions for the board.
- *
- * @ingroup GPIO
- */
-
-static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = {
-	{		/* SD1 WP */
-	 MX50_PIN_ECSPI2_SS0, IOMUX_CONFIG_GPIO,
-	 },
-	{		/* SD1 CD */
-	 MX50_PIN_EIM_CRE, IOMUX_CONFIG_GPIO,
-	 },
-	{		/* SD1 CMD */
-	 MX50_PIN_SD1_CMD, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
-	 },
-	{		/* SD1 CLK */
-	 MX50_PIN_SD1_CLK, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
-	 },
-	{		/* SD1 D0 */
-	 MX50_PIN_SD1_D0, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
-	 },
-	{		/* SD1 D1 */
-	 MX50_PIN_SD1_D1, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
-	 },
-	{		/* SD1 D2 */
-	 MX50_PIN_SD1_D2, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
-	 },
-	{		/* SD1 D3 */
-	 MX50_PIN_SD1_D3, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
-	 },
-	{		/* SD2 CD */
-	 MX50_PIN_SD2_CD, IOMUX_CONFIG_GPIO,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
-	 },
-	{		/* SD2 WP */
-	 MX50_PIN_SD2_WP, IOMUX_CONFIG_GPIO,
-	 },
-	{		/* SD2 CMD */
-	 MX50_PIN_SD2_CMD, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
-	 },
-	{		/* SD2 CLK */
-	 MX50_PIN_SD2_CLK, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
-	 },
-	{		/* SD2 D0 */
-	 MX50_PIN_SD2_D0, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
-	 },
-	{		/* SD2 D1 */
-	 MX50_PIN_SD2_D1, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
-	 },
-	{		/* SD2 D2 */
-	 MX50_PIN_SD2_D2, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
-	 },
-	{		/* SD2 D3 */
-	 MX50_PIN_SD2_D3, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
-	 },
-	{		/* SD2 D4 */
-	 MX50_PIN_SD2_D4, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
-	 },
-	{		/* SD2 D5 */
-	 MX50_PIN_SD2_D5, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
-	 },
-	{		/* SD2 D6 */
-	 MX50_PIN_SD2_D6, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
-	 },
-	{		/* SD2 D7 */
-	 MX50_PIN_SD2_D7, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
-	 },
-	{		/* SD3 CD */
-	 MX50_PIN_KEY_COL2, IOMUX_CONFIG_GPIO,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST),
-	 },
-	{		/* SD3 WP */
-	 MX50_PIN_SD3_WP, IOMUX_CONFIG_GPIO,
-	 },
-	{		/* SD3 CMD */
-	 MX50_PIN_SD3_CMD, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
-	 PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH),
-	 },
-	{		/* SD3 CLK */
-	 MX50_PIN_SD3_CLK, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | PAD_CTL_47K_PU |
-	 PAD_CTL_DRV_HIGH),
-	 },
-	{		/* SD3 D0 */
-	 MX50_PIN_SD3_D0, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
-	 PAD_CTL_47K_PU | PAD_CTL_DRV_HIGH),
-	 },
-	{		/* SD3 D1 */
-	 MX50_PIN_SD3_D1, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
-	 PAD_CTL_47K_PU | PAD_CTL_DRV_HIGH),
-	 },
-	{		/* SD3 D2 */
-	 MX50_PIN_SD3_D2, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
-	 PAD_CTL_47K_PU | PAD_CTL_DRV_HIGH),
-	 },
-	{		/* SD3 D3 */
-	 MX50_PIN_SD3_D3, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
-	 PAD_CTL_47K_PU | PAD_CTL_DRV_HIGH),
-	 },
-	{		/* SD3 D4 */
-	 MX50_PIN_SD3_D4, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
-	 PAD_CTL_47K_PU | PAD_CTL_DRV_HIGH),
-	 },
-	{		/* SD3 D5 */
-	 MX50_PIN_SD3_D5, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
-	 PAD_CTL_47K_PU | PAD_CTL_DRV_HIGH),
-	 },
-	{		/* SD3 D6 */
-	 MX50_PIN_SD3_D6, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
-	 PAD_CTL_47K_PU | PAD_CTL_DRV_HIGH),
-	 },
-	{		/* SD3 D7 */
-	 MX50_PIN_SD3_D7, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
-	 PAD_CTL_47K_PU | PAD_CTL_DRV_HIGH),
-	 },
-
-	{
-	 MX50_PIN_SSI_TXD, IOMUX_CONFIG_ALT0,
-	 },
-	{
-	 MX50_PIN_SSI_RXD, IOMUX_CONFIG_ALT0,
-	 },
-	{
-	 MX50_PIN_SSI_TXC, IOMUX_CONFIG_ALT0,
-	 },
-	{
-	 MX50_PIN_SSI_TXFS, IOMUX_CONFIG_ALT0,
-	 },
-	/* LINE1_DETECT (headphone detect) */
-	{
-	 MX50_PIN_ECSPI1_SS0, IOMUX_CONFIG_GPIO, PAD_CTL_100K_PU,
-	 },
-	{
-	 MX50_PIN_ECSPI2_MISO, IOMUX_CONFIG_GPIO, PAD_CTL_100K_PU,
-	 },
-	 /* UART pad setting */
-	{
-	 MX50_PIN_UART1_TXD, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_PUE_KEEPER |
-	 PAD_CTL_PKE_ENABLE | PAD_CTL_ODE_OPENDRAIN_NONE),
-	 },
-	{
-	 MX50_PIN_UART1_RXD, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_PUE_KEEPER |
-	 PAD_CTL_PKE_ENABLE | PAD_CTL_ODE_OPENDRAIN_NONE),
-	 MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
-	 INPUT_CTL_PATH1,
-	},
-	{
-	 MX50_PIN_UART1_CTS, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_PUE_KEEPER |
-	 PAD_CTL_PKE_ENABLE | PAD_CTL_ODE_OPENDRAIN_NONE),
-	 },
-	{
-	 MX50_PIN_UART1_RTS, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_PUE_KEEPER |
-	 PAD_CTL_PKE_ENABLE | PAD_CTL_ODE_OPENDRAIN_NONE),
-	  MUX_IN_UART1_IPP_UART_RTS_B_SELECT_INPUT,
-	 INPUT_CTL_PATH1,
-	},
-	{
-	 MX50_PIN_UART2_TXD, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_PUE_KEEPER |
-	 PAD_CTL_PKE_ENABLE | PAD_CTL_ODE_OPENDRAIN_NONE),
-	 },
-	{
-	 MX50_PIN_UART2_RXD, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_PUE_KEEPER |
-	 PAD_CTL_PKE_ENABLE | PAD_CTL_ODE_OPENDRAIN_NONE),
-	 MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,
-	 INPUT_CTL_PATH1,
-	},
-	{
-	 MX50_PIN_UART2_CTS, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_PUE_KEEPER |
-	 PAD_CTL_PKE_ENABLE | PAD_CTL_ODE_OPENDRAIN_NONE),
-	 },
-	{
-	 MX50_PIN_UART2_RTS, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_DRV_HIGH | PAD_CTL_PUE_KEEPER |
-	 PAD_CTL_PKE_ENABLE | PAD_CTL_ODE_OPENDRAIN_NONE),
-	 MUX_IN_UART2_IPP_UART_RTS_B_SELECT_INPUT,
-	 INPUT_CTL_PATH1,
-	},
-	{ /* I2C1 SDA */
-	 MX50_PIN_I2C1_SDA, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
-	 (PAD_CTL_SRE_FAST | PAD_CTL_ODE_OPENDRAIN_ENABLE |
-	 PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
-	 PAD_CTL_HYS_ENABLE),
-	 },
-	{ /* I2C1 SCL */
-	 MX50_PIN_I2C1_SCL, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
-	 (PAD_CTL_SRE_FAST | PAD_CTL_ODE_OPENDRAIN_ENABLE |
-	 PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
-	 PAD_CTL_HYS_ENABLE),
-	 },
-	{ /* I2C2 SDA */
-	 MX50_PIN_I2C2_SDA, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
-	 (PAD_CTL_SRE_FAST | PAD_CTL_ODE_OPENDRAIN_ENABLE |
-	 PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
-	 PAD_CTL_HYS_ENABLE),
-	 },
-	{ /* I2C2 SCL */
-	 MX50_PIN_I2C2_SCL, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
-	 (PAD_CTL_SRE_FAST | PAD_CTL_ODE_OPENDRAIN_ENABLE |
-	 PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
-	 PAD_CTL_HYS_ENABLE),
-	 },
-	{ /* I2C3 SDA */
-	 MX50_PIN_I2C3_SDA, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
-	 (PAD_CTL_SRE_FAST | PAD_CTL_ODE_OPENDRAIN_ENABLE |
-	 PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
-	 PAD_CTL_HYS_ENABLE),
-	 },
-	{ /* I2C3 SCL */
-	 MX50_PIN_I2C3_SCL, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
-	 (PAD_CTL_SRE_FAST | PAD_CTL_ODE_OPENDRAIN_ENABLE |
-	 PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
-	 PAD_CTL_HYS_ENABLE),
-	 },
-	 /* EPDC pins */
-	{ /* EPDC D0 */
-	 MX50_PIN_EPDC_D0, IOMUX_CONFIG_ALT0,
-	 },
-	{ /* EPDC D1 */
-	 MX50_PIN_EPDC_D1, IOMUX_CONFIG_ALT0,
-	 },
-	{ /* EPDC D2 */
-	 MX50_PIN_EPDC_D2, IOMUX_CONFIG_ALT0,
-	 },
-	{ /* EPDC D3 */
-	 MX50_PIN_EPDC_D3, IOMUX_CONFIG_ALT0,
-	 },
-	{ /* EPDC D4 */
-	 MX50_PIN_EPDC_D4, IOMUX_CONFIG_ALT0,
-	 },
-	{ /* EPDC D5 */
-	 MX50_PIN_EPDC_D5, IOMUX_CONFIG_ALT0,
-	 },
-	{ /* EPDC D6 */
-	 MX50_PIN_EPDC_D6, IOMUX_CONFIG_ALT0,
-	 },
-	{ /* EPDC D7 */
-	 MX50_PIN_EPDC_D7, IOMUX_CONFIG_ALT0,
-	 },
-	{ /* EPDC GDCLK */
-	 MX50_PIN_EPDC_GDCLK, IOMUX_CONFIG_ALT0,
-	 },
-	{ /* EPDC GDSP */
-	 MX50_PIN_EPDC_GDSP, IOMUX_CONFIG_ALT0,
-	 },
-	{ /* EPDC GDOE */
-	 MX50_PIN_EPDC_GDOE, IOMUX_CONFIG_ALT0,
-	 },
-	{ /* EPDC GDRL */
-	 MX50_PIN_EPDC_GDRL, IOMUX_CONFIG_ALT0,
-	 },
-	{ /* EPDC SDCLK */
-	 MX50_PIN_EPDC_SDCLK, IOMUX_CONFIG_ALT0,
-	 },
-	{ /* EPDC SDOE */
-	 MX50_PIN_EPDC_SDOE, IOMUX_CONFIG_ALT0,
-	 },
-	{ /* EPDC SDLE */
-	 MX50_PIN_EPDC_SDLE, IOMUX_CONFIG_ALT0,
-	 },
-	{ /* EPDC SDSHR */
-	 MX50_PIN_EPDC_SDSHR, IOMUX_CONFIG_ALT0,
-	 },
-	{ /* EPDC BDR0 */
-	 MX50_PIN_EPDC_BDR0, IOMUX_CONFIG_ALT0,
-	 },
-	{ /* EPDC SDCE0 */
-	 MX50_PIN_EPDC_SDCE0, IOMUX_CONFIG_ALT0,
-	 },
-	{ /* EPDC SDCE1 */
-	 MX50_PIN_EPDC_SDCE1, IOMUX_CONFIG_ALT0,
-	 },
-	{ /* EPDC SDCE2 */
-	 MX50_PIN_EPDC_SDCE2, IOMUX_CONFIG_ALT0,
-	 },
-	 /* EPD PMIC pins */
-	{ /* EPDC PWRSTAT - GPIO3[28] for PWR_GOOD status */
-	 MX50_PIN_EPDC_PWRSTAT, IOMUX_CONFIG_ALT1,
-	 },
-	{ /* EPDC VCOM0 - GPIO4[21] for VCOM control */
-	 MX50_PIN_EPDC_VCOM0, IOMUX_CONFIG_ALT1,
-	 },
-	{ /* ELCDIF D8 */
-	 MX50_PIN_DISP_D8, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
-	  PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH),
-	 },
-	{ /* ELCDIF D9 */
-	 MX50_PIN_DISP_D9, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
-	  PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH),
-	 },
-	{ /* ELCDIF D10 */
-	 MX50_PIN_DISP_D10, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
-	  PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH),
-	 },
-	{ /* ELCDIF D11 */
-	 MX50_PIN_DISP_D11, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
-	  PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH),
-	 },
-	{ /* ELCDIF D12 */
-	 MX50_PIN_DISP_D12, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
-	  PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH),
-	 },
-	{ /* ELCDIF D13 */
-	 MX50_PIN_DISP_D13, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
-	  PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH),
-	 },
-	{ /* ELCDIF D14 */
-	 MX50_PIN_DISP_D14, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
-	  PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH),
-	 },
-	{ /* ELCDIF D15 */
-	 MX50_PIN_DISP_D15, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
-	  PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH),
-	 },
-	{ /* ELCDIF VSYNC */
-	 MX50_PIN_DISP_RS, IOMUX_CONFIG_ALT2,
-	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
-	  PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH),
-	 },
-	{ /* ELCDIF contrast */
-	 MX50_PIN_DISP_BUSY, IOMUX_CONFIG_ALT1,
-	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
-	  PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH),
-	 },
-	{ /* ELCDIF HSYNC */
-	 MX50_PIN_DISP_CS, IOMUX_CONFIG_ALT2,
-	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
-	  PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH),
-	 },
-	{ /* ELCDIF DRDY */
-	 MX50_PIN_DISP_RD, IOMUX_CONFIG_ALT2,
-	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
-	  PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH),
-	 },
-	{ /* ELCDIF PIXCLK */
-	 MX50_PIN_DISP_WR, IOMUX_CONFIG_ALT2,
-	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
-	  PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH),
-	 },
-	{ /* UART4 TXD - GPIO6[16] for EPD PMIC WAKEUP */
-	 MX50_PIN_UART4_TXD, IOMUX_CONFIG_ALT1,
-	 },
-	{ /* UART4 RXD - GPIO6[17] for EPD PMIC intr */
-	 MX50_PIN_UART4_RXD, IOMUX_CONFIG_ALT1,
-	 },
-	/* USB_H1_PWR */
-	{
-	 MX50_PIN_EPITO, IOMUX_CONFIG_ALT2,
-	 PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH,
-	},
-	/* FIXME: USB_H1_OC, need to comment below line if
-	 * one needs to debug owire.
-	 */
-	{
-	 MX50_PIN_OWIRE, IOMUX_CONFIG_ALT2,
-	 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU,
-	},
-	/* USB_OTG_PWR */
-	{
-	 MX50_PIN_PWM2, IOMUX_CONFIG_ALT2,
-	 PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH,
-	},
-	/*
-	 * Set USB_OTG_OC, the pad value is the default value
-	 * according to IC suggestion.
-	 */
-	{
-	 MX50_PIN_PWM1, IOMUX_CONFIG_ALT2,
-	 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU,
-	 MUX_IN_USBOH1_IPP_IND_OTG_OC_SELECT_INPUT, INPUT_CTL_PATH1,
-	},
-	{ /* FEC_MDIO */
-	 MX50_PIN_SSI_RXC, IOMUX_CONFIG_ALT6,
-	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
-	  PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE | PAD_CTL_DRV_HIGH),
-	 MUX_IN_FEC_FEC_MDI_SELECT_INPUT,
-	 INPUT_CTL_PATH1,
-	 },
-	{ /* FEC_TX_CLK */
-	 MX50_PIN_DISP_D0, IOMUX_CONFIG_ALT2,
-	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE),
-	 },
-	{ /* FEC_RX_ER */
-	 MX50_PIN_DISP_D1, IOMUX_CONFIG_ALT2,
-	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE),
-	 MUX_IN_FEC_FEC_RX_ER_SELECT_INPUT,
-	 INPUT_CTL_PATH0,
-	 },
-	{ /* FEC_CRS_DV */
-	 MX50_PIN_DISP_D2, IOMUX_CONFIG_ALT2,
-	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE),
-	 MUX_IN_FEC_FEC_RX_DV_SELECT_INPUT,
-	 INPUT_CTL_PATH0,
-	 },
-	{ /* FEC_RXD1 */
-	 MX50_PIN_DISP_D3, IOMUX_CONFIG_ALT2,
-	 (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE),
-	 MUX_IN_FEC_FEC_RDATA_1_SELECT_INPUT,
-	 INPUT_CTL_PATH0,
-	 },
-	{ /* FEC_RXD0 */
-	 MX50_PIN_DISP_D4, IOMUX_CONFIG_ALT2,
-	(PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE),
-	 MUX_IN_FEC_FEC_RDATA_0_SELECT_INPUT,
-	 INPUT_CTL_PATH0,
-	 },
-	{ /* FEC_TX_EN */
-	 MX50_PIN_DISP_D5, IOMUX_CONFIG_ALT2,
-	 PAD_CTL_DRV_HIGH,
-	 },
-	{ /* FEC_TXD1 */
-	 MX50_PIN_DISP_D6, IOMUX_CONFIG_ALT2,
-	 PAD_CTL_DRV_HIGH,
-	 },
-	{ /* FEC_TXD0 */
-	 MX50_PIN_DISP_D7, IOMUX_CONFIG_ALT2,
-	 PAD_CTL_DRV_HIGH,
-	 },
-	{ /* FEC_MDC */
-	 MX50_PIN_SSI_RXFS, IOMUX_CONFIG_ALT6,
-	 PAD_CTL_DRV_HIGH,
-	 },
-	{ /* CSPI SS0 */
-	 MX50_PIN_CSPI_SS0, IOMUX_CONFIG_ALT0,
-	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH),
-	 },
-	{ /* CSPI SS1 */
-	 MX50_PIN_ECSPI1_MOSI, IOMUX_CONFIG_ALT2,
-	 (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
-	  PAD_CTL_22K_PU | PAD_CTL_DRV_HIGH),
-	 },
-	{
-	 MX50_PIN_CSPI_MOSI, IOMUX_CONFIG_ALT0,
-	 },
-	{
-	 MX50_PIN_CSPI_MISO, IOMUX_CONFIG_ALT0,
-	 },
-	{
-	 MX50_PIN_CSPI_SCLK, IOMUX_CONFIG_ALT0,
-	 },
-};
-
-static int __initdata enable_w1 = { 0 };
-static int __init w1_setup(char *__unused)
-{
-	enable_w1 = 1;
-	return cpu_is_mx50();
-}
-
-__setup("w1", w1_setup);
-
-void __init mx50_arm2_io_init(void)
-{
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(mxc_iomux_pins); i++) {
-		mxc_request_iomux(mxc_iomux_pins[i].pin,
-				  mxc_iomux_pins[i].mux_mode);
-		if (mxc_iomux_pins[i].pad_cfg)
-			mxc_iomux_set_pad(mxc_iomux_pins[i].pin,
-					  mxc_iomux_pins[i].pad_cfg);
-		if (mxc_iomux_pins[i].in_select)
-			mxc_iomux_set_input(mxc_iomux_pins[i].in_select,
-					    mxc_iomux_pins[i].in_mode);
-	}
-
-	/* SD1 WP */
-	gpio_request(IOMUX_TO_GPIO(MX50_PIN_ECSPI2_SS0), "ecspi2_ss0");
-	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_ECSPI2_SS0));
-
-	/* SD1 CD */
-	gpio_request(IOMUX_TO_GPIO(MX50_PIN_EIM_CRE), "eim_cre");
-	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_EIM_CRE));
-
-	/* SD2 WP */
-	gpio_request(IOMUX_TO_GPIO(MX50_PIN_SD2_WP), "sd2_wp");
-	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_SD2_WP));
-
-	/* SD2 CD */
-	gpio_request(IOMUX_TO_GPIO(MX50_PIN_SD2_CD), "sd2_cd");
-	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_SD2_CD));
-
-	/* SD3 WP */
-	gpio_request(IOMUX_TO_GPIO(MX50_PIN_SD3_WP), "sd3_wp");
-	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_SD2_WP));
-
-	/* SD3 CD */
-	gpio_request(IOMUX_TO_GPIO(MX50_PIN_KEY_COL2), "key_col2");
-	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_KEY_COL2));
-
-	/* LINE1_DETECT (headphone detect) */
-	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_ECSPI1_SS0));
-
-	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_ECSPI2_MISO));
-
-	/* EPDC PMIC */
-	gpio_request(IOMUX_TO_GPIO(MX50_PIN_UART4_TXD), "uart4_txd");
-	gpio_direction_output(IOMUX_TO_GPIO(MX50_PIN_UART4_TXD), 0);
-
-	gpio_request(IOMUX_TO_GPIO(MX50_PIN_EPDC_VCOM0), "epdc_vcom");
-	gpio_direction_output(IOMUX_TO_GPIO(MX50_PIN_EPDC_VCOM0), 0);
-
-	gpio_request(IOMUX_TO_GPIO(MX50_PIN_UART4_RXD), "uart4_rxd");
-	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_UART4_RXD));
-
-	gpio_request(IOMUX_TO_GPIO(MX50_PIN_EPDC_PWRSTAT), "epdc_pwrstat");
-	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_EPDC_PWRSTAT));
-
-	/* ELCDIF backlight */
-	gpio_request(IOMUX_TO_GPIO(MX50_PIN_DISP_BUSY), "gp2_18");
-	gpio_direction_output(IOMUX_TO_GPIO(MX50_PIN_DISP_BUSY), 1);
-
-	if (enable_w1) {
-		/* OneWire */
-		mxc_request_iomux(MX50_PIN_OWIRE, IOMUX_CONFIG_ALT0);
-		mxc_iomux_set_pad(MX50_PIN_OWIRE, PAD_CTL_HYS_ENABLE |
-						  PAD_CTL_PKE_ENABLE |
-						  PAD_CTL_ODE_OPENDRAIN_ENABLE |
-						  PAD_CTL_DRV_HIGH |
-						  PAD_CTL_SRE_FAST |
-						  PAD_CTL_100K_PU |
-						  PAD_CTL_PUE_PULL);
-	}
-}
-
-/* workaround for cspi chipselect pin may not keep correct level when idle */
-void mx50_arm2_gpio_spi_chipselect_active(int cspi_mode, int status,
-					     int chipselect)
-{
-	switch (cspi_mode) {
-	case 1:
-		break;
-	case 2:
-		break;
-	case 3:
-		switch (chipselect) {
-		case 0x1:
-			/* enable ss0 */
-			mxc_request_iomux(MX50_PIN_CSPI_SS0, IOMUX_CONFIG_ALT0);
-			/*disable other ss */
-			mxc_request_iomux(MX50_PIN_ECSPI1_MOSI, IOMUX_CONFIG_GPIO);
-			/* pull up/down deassert it */
-			gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_ECSPI1_MOSI));
-			break;
-		case 0x2:
-			/* enable ss1 */
-			mxc_request_iomux(MX50_PIN_ECSPI1_MOSI, IOMUX_CONFIG_ALT2);
-			/*disable other ss */
-			mxc_request_iomux(MX50_PIN_CSPI_SS0, IOMUX_CONFIG_GPIO);
-			/* pull up/down deassert it */
-			gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_CSPI_SS0));
-			break;
-		default:
-			break;
-		}
-		break;
-
-	default:
-		break;
-	}
-}
-
-void mx50_arm2_gpio_spi_chipselect_inactive(int cspi_mode, int status,
-					       int chipselect)
-{
-	switch (cspi_mode) {
-	case 1:
-		break;
-	case 2:
-		break;
-	case 3:
-		switch (chipselect) {
-		case 0x1:
-			mxc_free_iomux(MX50_PIN_ECSPI1_MOSI, IOMUX_CONFIG_GPIO);
-			break;
-		case 0x2:
-			mxc_free_iomux(MX50_PIN_CSPI_SS0, IOMUX_CONFIG_GPIO);
-			break;
-		default:
-			break;
-		}
-		break;
-	default:
-		break;
-	}
-
-}
diff --git a/arch/arm/mach-mx5/mx50_arm2_pmic_mc13892.c b/arch/arm/mach-mx5/mx50_arm2_pmic_mc13892.c
index 9b97fece73d8..66972b19d9ab 100644
--- a/arch/arm/mach-mx5/mx50_arm2_pmic_mc13892.c
+++ b/arch/arm/mach-mx5/mx50_arm2_pmic_mc13892.c
@@ -27,8 +27,8 @@
 #include <linux/regulator/machine.h>
 #include <linux/mfd/mc13892/core.h>
 #include <mach/irqs.h>
-#include "iomux.h"
-#include "mx50_pins.h"
+
+#include <mach/iomux-mx50.h>
 
 /*
  * Convenience conversion.
@@ -405,7 +405,7 @@ static struct mc13892_platform_data mc13892_plat = {
 
 static struct spi_board_info __initdata mc13892_spi_device = {
 	.modalias = "pmic_spi",
-	.irq = IOMUX_TO_IRQ(MX50_PIN_ECSPI2_MISO),
+	.irq = IOMUX_TO_IRQ_V3(114),
 	.max_speed_hz = 6000000,	/* max spi SCK clock speed in HZ */
 	.bus_num = 3,
 	.chip_select = 0,
diff --git a/arch/arm/mach-mx5/mx50_pins.h b/arch/arm/mach-mx5/mx50_pins.h
deleted file mode 100644
index 75d654442429..000000000000
--- a/arch/arm/mach-mx5/mx50_pins.h
+++ /dev/null
@@ -1,340 +0,0 @@
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-#ifndef __ASM_ARCH_MXC_MX50_PINS_H__
-#define __ASM_ARCH_MXC_MX50_PINS_H__
-#include "iomux.h"
-
-/*!
- * @file mach-mx5/mx50_pins.h
- *
- * @brief MX50 I/O Pin List
- *
- * @ingroup GPIO_MX50
- */
-
-#ifndef __ASSEMBLY__
-
-#define PAD_I_START_MX50		0x2CC
-
-#define _MXC_BUILD_PIN_MX50(gp, gi, ga, mi, pi) \
-	(((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \
-	((mi) << MUX_I) | \
-	((pi - PAD_I_START_MX50) << PAD_I) | \
-	((ga) << GPIO_I))
-
-#define _MXC_BUILD_GPIO_PIN_MX50(gp, gi, ga, mi, pi) \
-    _MXC_BUILD_PIN_MX50(gp, gi, ga, mi, pi)
-
-#define _MXC_BUILD_NON_GPIO_PIN_MX50(mi, pi) \
-    _MXC_BUILD_PIN_MX50(NON_GPIO_PORT, 0, 0, mi, pi)
-/*!
- * This enumeration is constructed based on the Section
- * "sw_pad_ctl & sw_mux_ctl details" of the MX50 IC Spec. Each enumerated
- * value is constructed based on the rules described above.
- */
-enum iomux_pins {
-	MX50_PIN_KEY_COL0 = _MXC_BUILD_GPIO_PIN_MX50(3, 0, 1, 0x20, 0x2CC),
-	MX50_PIN_KEY_ROW0 = _MXC_BUILD_GPIO_PIN_MX50(3, 1, 1, 0x24, 0x2D0),
-	MX50_PIN_KEY_COL1 = _MXC_BUILD_GPIO_PIN_MX50(3, 2, 1, 0x28, 0x2D4),
-	MX50_PIN_KEY_ROW1 = _MXC_BUILD_GPIO_PIN_MX50(3, 3, 1, 0x2C, 0x2D8),
-	MX50_PIN_KEY_COL2 = _MXC_BUILD_GPIO_PIN_MX50(3, 4, 1, 0x30, 0x2DC),
-	MX50_PIN_KEY_ROW2 = _MXC_BUILD_GPIO_PIN_MX50(3, 5, 1, 0x34, 0x2E0),
-	MX50_PIN_KEY_COL3 = _MXC_BUILD_GPIO_PIN_MX50(3, 6, 1, 0x38, 0x2E4),
-	MX50_PIN_KEY_ROW3 = _MXC_BUILD_GPIO_PIN_MX50(3, 7, 1, 0x3C, 0x2E8),
-	MX50_PIN_I2C1_SCL = _MXC_BUILD_GPIO_PIN_MX50(5, 18, 1, 0x40, 0x2EC),
-	MX50_PIN_I2C1_SDA = _MXC_BUILD_GPIO_PIN_MX50(5, 19, 1, 0x44, 0x2F0),
-	MX50_PIN_I2C2_SCL = _MXC_BUILD_GPIO_PIN_MX50(5, 20, 1, 0x48, 0x2F4),
-	MX50_PIN_I2C2_SDA = _MXC_BUILD_GPIO_PIN_MX50(5, 21, 1, 0x4C, 0x2F8),
-	MX50_PIN_I2C3_SCL = _MXC_BUILD_GPIO_PIN_MX50(5, 22, 1, 0x50, 0x2FC),
-	MX50_PIN_I2C3_SDA = _MXC_BUILD_GPIO_PIN_MX50(5, 23, 1, 0x54, 0x300),
-	MX50_PIN_PWM1 = _MXC_BUILD_GPIO_PIN_MX50(5, 24, 1, 0x58, 0x304),
-	MX50_PIN_PWM2 = _MXC_BUILD_GPIO_PIN_MX50(5, 25, 1, 0x5C, 0x308),
-	MX50_PIN_OWIRE = _MXC_BUILD_GPIO_PIN_MX50(5, 26, 1, 0x60, 0x30C),
-	MX50_PIN_EPITO = _MXC_BUILD_GPIO_PIN_MX50(5, 27, 1, 0x64, 0x310),
-	MX50_PIN_WDOG = _MXC_BUILD_GPIO_PIN_MX50(5, 28, 1, 0x68, 0x314),
-	MX50_PIN_SSI_TXFS = _MXC_BUILD_GPIO_PIN_MX50(5, 0, 1, 0x6C, 0x318),
-	MX50_PIN_SSI_TXC = _MXC_BUILD_GPIO_PIN_MX50(5, 1, 1, 0x70, 0x31C),
-	MX50_PIN_SSI_TXD = _MXC_BUILD_GPIO_PIN_MX50(5, 2, 1, 0x74, 0x320),
-	MX50_PIN_SSI_RXD = _MXC_BUILD_GPIO_PIN_MX50(5, 3, 1, 0x78, 0x324),
-	MX50_PIN_SSI_RXFS = _MXC_BUILD_GPIO_PIN_MX50(5, 4, 1, 0x7C, 0x328),
-	MX50_PIN_SSI_RXC = _MXC_BUILD_GPIO_PIN_MX50(5, 5, 1, 0x80, 0x32C),
-	MX50_PIN_UART1_TXD = _MXC_BUILD_GPIO_PIN_MX50(5, 6, 1, 0x84, 0x330),
-	MX50_PIN_UART1_RXD = _MXC_BUILD_GPIO_PIN_MX50(5, 7, 1, 0x88, 0x334),
-	MX50_PIN_UART1_CTS = _MXC_BUILD_GPIO_PIN_MX50(5, 8, 1, 0x8C, 0x338),
-	MX50_PIN_UART1_RTS = _MXC_BUILD_GPIO_PIN_MX50(5, 9, 1, 0x90, 0x33C),
-	MX50_PIN_UART2_TXD = _MXC_BUILD_GPIO_PIN_MX50(5, 10, 1, 0x94, 0x340),
-	MX50_PIN_UART2_RXD = _MXC_BUILD_GPIO_PIN_MX50(5, 11, 1, 0x98, 0x344),
-	MX50_PIN_UART2_CTS = _MXC_BUILD_GPIO_PIN_MX50(5, 12, 1, 0x9C, 0x348),
-	MX50_PIN_UART2_RTS = _MXC_BUILD_GPIO_PIN_MX50(5, 13, 1, 0xA0, 0x34C),
-	MX50_PIN_UART3_TXD = _MXC_BUILD_GPIO_PIN_MX50(5, 14, 1, 0xA4, 0x350),
-	MX50_PIN_UART3_RXD = _MXC_BUILD_GPIO_PIN_MX50(5, 15, 1, 0xA8, 0x354),
-	MX50_PIN_UART4_TXD = _MXC_BUILD_GPIO_PIN_MX50(5, 16, 1, 0xAC, 0x358),
-	MX50_PIN_UART4_RXD = _MXC_BUILD_GPIO_PIN_MX50(5, 17, 1, 0xB0, 0x35C),
-	MX50_PIN_CSPI_SCLK = _MXC_BUILD_GPIO_PIN_MX50(3, 8, 1, 0xB4, 0x360),
-	MX50_PIN_CSPI_MOSI = _MXC_BUILD_GPIO_PIN_MX50(3, 9, 1, 0xB8, 0x364),
-	MX50_PIN_CSPI_MISO = _MXC_BUILD_GPIO_PIN_MX50(3, 10, 1, 0xBC, 0x368),
-	MX50_PIN_CSPI_SS0 = _MXC_BUILD_GPIO_PIN_MX50(3, 11, 1, 0xC0, 0x36C),
-	MX50_PIN_ECSPI1_SCLK = _MXC_BUILD_GPIO_PIN_MX50(3, 12, 1, 0xC4, 0x370),
-	MX50_PIN_ECSPI1_MOSI = _MXC_BUILD_GPIO_PIN_MX50(3, 13, 1, 0xC8, 0x374),
-	MX50_PIN_ECSPI1_MISO = _MXC_BUILD_GPIO_PIN_MX50(3, 14, 1, 0xCC, 0x378),
-	MX50_PIN_ECSPI1_SS0 = _MXC_BUILD_GPIO_PIN_MX50(3, 15, 1, 0xD0, 0x37C),
-	MX50_PIN_ECSPI2_SCLK = _MXC_BUILD_GPIO_PIN_MX50(3, 16, 1, 0xD4, 0x380),
-	MX50_PIN_ECSPI2_MOSI = _MXC_BUILD_GPIO_PIN_MX50(3, 17, 1, 0xD8, 0x384),
-	MX50_PIN_ECSPI2_MISO = _MXC_BUILD_GPIO_PIN_MX50(3, 18, 1, 0xDC, 0x388),
-	MX50_PIN_ECSPI2_SS0 = _MXC_BUILD_GPIO_PIN_MX50(3, 19, 1, 0xE0, 0x38C),
-	MX50_PIN_SD1_CLK = _MXC_BUILD_GPIO_PIN_MX50(4, 0, 1, 0xE4, 0x390),
-	MX50_PIN_SD1_CMD = _MXC_BUILD_GPIO_PIN_MX50(4, 1, 1, 0xE8, 0x394),
-	MX50_PIN_SD1_D0 = _MXC_BUILD_GPIO_PIN_MX50(4, 2, 1, 0xEC, 0x398),
-	MX50_PIN_SD1_D1 = _MXC_BUILD_GPIO_PIN_MX50(4, 3, 1, 0xF0, 0x39C),
-	MX50_PIN_SD1_D2 = _MXC_BUILD_GPIO_PIN_MX50(4, 4, 1, 0xF4, 0x3A0),
-	MX50_PIN_SD1_D3 = _MXC_BUILD_GPIO_PIN_MX50(4, 5, 1, 0xF8, 0x3A4),
-	MX50_PIN_SD2_CLK = _MXC_BUILD_GPIO_PIN_MX50(4, 6, 1, 0xFC, 0x3A8),
-	MX50_PIN_SD2_CMD = _MXC_BUILD_GPIO_PIN_MX50(4, 7, 1, 0x100, 0x3AC),
-	MX50_PIN_SD2_D0 = _MXC_BUILD_GPIO_PIN_MX50(4, 8, 1, 0x104, 0x3B0),
-	MX50_PIN_SD2_D1 = _MXC_BUILD_GPIO_PIN_MX50(4, 9, 1, 0x108, 0x3B4),
-	MX50_PIN_SD2_D2 = _MXC_BUILD_GPIO_PIN_MX50(4, 10, 1, 0x10C, 0x3B8),
-	MX50_PIN_SD2_D3 = _MXC_BUILD_GPIO_PIN_MX50(4, 11, 1, 0x110, 0x3BC),
-	MX50_PIN_SD2_D4 = _MXC_BUILD_GPIO_PIN_MX50(4, 12, 1, 0x114, 0x3C0),
-	MX50_PIN_SD2_D5 = _MXC_BUILD_GPIO_PIN_MX50(4, 13, 1, 0x118, 0x3C4),
-	MX50_PIN_SD2_D6 = _MXC_BUILD_GPIO_PIN_MX50(4, 14, 1, 0x11C, 0x3C8),
-	MX50_PIN_SD2_D7 = _MXC_BUILD_GPIO_PIN_MX50(4, 15, 1, 0x120, 0x3CC),
-	MX50_PIN_SD2_WP = _MXC_BUILD_GPIO_PIN_MX50(4, 16, 1, 0x124, 0x3D0),
-	MX50_PIN_SD2_CD = _MXC_BUILD_GPIO_PIN_MX50(4, 17, 1, 0x128, 0x3D4),
-
-	MX50_PIN_PMIC_ON_REQ = _MXC_BUILD_NON_GPIO_PIN_MX50(NON_MUX_I, 0x3D8),
-	MX50_PIN_PMIC_STBY_REQ = _MXC_BUILD_NON_GPIO_PIN_MX50(NON_MUX_I, 0x3DC),
-	MX50_PIN_PMIC_PORT_B = _MXC_BUILD_NON_GPIO_PIN_MX50(NON_MUX_I, 0x3E0),
-	MX50_PIN_PMIC_BOOT_MODE1 = _MXC_BUILD_NON_GPIO_PIN_MX50(NON_MUX_I, 0x3E4),
-	MX50_PIN_PMIC_RESET_IN_B = _MXC_BUILD_NON_GPIO_PIN_MX50(NON_MUX_I, 0x3E8),
-	MX50_PIN_PMIC_BOOT_MODE0 = _MXC_BUILD_NON_GPIO_PIN_MX50(NON_MUX_I, 0x3EC),
-	MX50_PIN_PMIC_TEST_MODE = _MXC_BUILD_NON_GPIO_PIN_MX50(NON_MUX_I, 0x3F0),
-	MX50_PIN_PMIC_JTAG_TMS = _MXC_BUILD_NON_GPIO_PIN_MX50(NON_MUX_I, 0x3F4),
-	MX50_PIN_PMIC_JTAG_MOD = _MXC_BUILD_NON_GPIO_PIN_MX50(NON_MUX_I, 0x3F8),
-	MX50_PIN_PMIC_JTAG_TRSTB = _MXC_BUILD_NON_GPIO_PIN_MX50(NON_MUX_I, 0x3FC),
-	MX50_PIN_PMIC_JTAG_TDI = _MXC_BUILD_NON_GPIO_PIN_MX50(NON_MUX_I, 0x400),
-	MX50_PIN_PMIC_JTAG_TCK = _MXC_BUILD_NON_GPIO_PIN_MX50(NON_MUX_I, 0x404),
-	MX50_PIN_PMIC_JTAG_TDO = _MXC_BUILD_NON_GPIO_PIN_MX50(NON_MUX_I, 0x408),
-
-	MX50_PIN_DISP_D0 = _MXC_BUILD_GPIO_PIN_MX50(1, 0, 1, 0x12C, 0x40C),
-	MX50_PIN_DISP_D1 = _MXC_BUILD_GPIO_PIN_MX50(1, 1, 1, 0x130, 0x410),
-	MX50_PIN_DISP_D2 = _MXC_BUILD_GPIO_PIN_MX50(1, 2, 1, 0x134, 0x414),
-	MX50_PIN_DISP_D3 = _MXC_BUILD_GPIO_PIN_MX50(1, 3, 1, 0x138, 0x418),
-	MX50_PIN_DISP_D4 = _MXC_BUILD_GPIO_PIN_MX50(1, 4, 1, 0x13C, 0x41C),
-	MX50_PIN_DISP_D5 = _MXC_BUILD_GPIO_PIN_MX50(1, 5, 1, 0x140, 0x420),
-	MX50_PIN_DISP_D6 = _MXC_BUILD_GPIO_PIN_MX50(1, 6, 1, 0x144, 0x424),
-	MX50_PIN_DISP_D7 = _MXC_BUILD_GPIO_PIN_MX50(1, 7, 1, 0x148, 0x428),
-	MX50_PIN_DISP_WR = _MXC_BUILD_GPIO_PIN_MX50(1, 16, 1, 0x14C, 0x42C),
-	MX50_PIN_DISP_RD = _MXC_BUILD_GPIO_PIN_MX50(1, 19, 1, 0x150, 0x430),
-	MX50_PIN_DISP_RS = _MXC_BUILD_GPIO_PIN_MX50(1, 17, 1, 0x154, 0x434),
-	MX50_PIN_DISP_CS = _MXC_BUILD_GPIO_PIN_MX50(1, 21, 1, 0x158, 0x438),
-	MX50_PIN_DISP_BUSY = _MXC_BUILD_GPIO_PIN_MX50(1, 18, 1, 0x15C, 0x43C),
-	MX50_PIN_DISP_RESET = _MXC_BUILD_GPIO_PIN_MX50(1, 20, 1, 0x160, 0x440),
-	MX50_PIN_SD3_CMD = _MXC_BUILD_GPIO_PIN_MX50(4, 18, 1, 0x164, 0x444),
-	MX50_PIN_SD3_CLK = _MXC_BUILD_GPIO_PIN_MX50(4, 19, 1, 0x168, 0x448),
-	MX50_PIN_SD3_D0 = _MXC_BUILD_GPIO_PIN_MX50(4, 20, 1, 0x16C, 0x44C),
-	MX50_PIN_SD3_D1 = _MXC_BUILD_GPIO_PIN_MX50(4, 21, 1, 0x170, 0x450),
-	MX50_PIN_SD3_D2 = _MXC_BUILD_GPIO_PIN_MX50(4, 22, 1, 0x174, 0x454),
-	MX50_PIN_SD3_D3 = _MXC_BUILD_GPIO_PIN_MX50(4, 23, 1, 0x178, 0x458),
-	MX50_PIN_SD3_D4 = _MXC_BUILD_GPIO_PIN_MX50(4, 24, 1, 0x17C, 0x45C),
-	MX50_PIN_SD3_D5 = _MXC_BUILD_GPIO_PIN_MX50(4, 25, 1, 0x180, 0x460),
-	MX50_PIN_SD3_D6 = _MXC_BUILD_GPIO_PIN_MX50(4, 26, 1, 0x184, 0x464),
-	MX50_PIN_SD3_D7 = _MXC_BUILD_GPIO_PIN_MX50(4, 27, 1, 0x188, 0x468),
-	MX50_PIN_SD3_WP = _MXC_BUILD_GPIO_PIN_MX50(4, 28, 1, 0x18C, 0x46C),
-	MX50_PIN_DISP_D8 = _MXC_BUILD_GPIO_PIN_MX50(1, 8, 1, 0x190, 0x470),
-	MX50_PIN_DISP_D9 = _MXC_BUILD_GPIO_PIN_MX50(1, 9, 1, 0x194, 0x474),
-	MX50_PIN_DISP_D10 = _MXC_BUILD_GPIO_PIN_MX50(1, 10, 1, 0x198, 0x478),
-	MX50_PIN_DISP_D11 = _MXC_BUILD_GPIO_PIN_MX50(1, 11, 1, 0x19C, 0x47C),
-	MX50_PIN_DISP_D12 = _MXC_BUILD_GPIO_PIN_MX50(1, 12, 1, 0x1A0, 0x480),
-	MX50_PIN_DISP_D13 = _MXC_BUILD_GPIO_PIN_MX50(1, 13, 1, 0x1A4, 0x484),
-	MX50_PIN_DISP_D14 = _MXC_BUILD_GPIO_PIN_MX50(1, 14, 1, 0x1A8, 0x488),
-	MX50_PIN_DISP_D15 = _MXC_BUILD_GPIO_PIN_MX50(1, 15, 1, 0x1AC, 0x48C),
-
-	MX50_PIN_EPDC_D0 = _MXC_BUILD_GPIO_PIN_MX50(2, 0, 1, 0x1B0, 0x54C),
-	MX50_PIN_EPDC_D1 = _MXC_BUILD_GPIO_PIN_MX50(2, 1, 1, 0x1B4, 0x550),
-	MX50_PIN_EPDC_D2 = _MXC_BUILD_GPIO_PIN_MX50(2, 2, 1, 0x1B8, 0x554),
-	MX50_PIN_EPDC_D3 = _MXC_BUILD_GPIO_PIN_MX50(2, 3, 1, 0x1BC, 0x558),
-	MX50_PIN_EPDC_D4 = _MXC_BUILD_GPIO_PIN_MX50(2, 4, 1, 0x1C0, 0x55C),
-	MX50_PIN_EPDC_D5 = _MXC_BUILD_GPIO_PIN_MX50(2, 5, 1, 0x1C4, 0x560),
-	MX50_PIN_EPDC_D6 = _MXC_BUILD_GPIO_PIN_MX50(2, 6, 1, 0x1C8, 0x564),
-	MX50_PIN_EPDC_D7 = _MXC_BUILD_GPIO_PIN_MX50(2, 7, 1, 0x1CC, 0x568),
-	MX50_PIN_EPDC_D8 = _MXC_BUILD_GPIO_PIN_MX50(2, 8, 1, 0x1D0, 0x56C),
-	MX50_PIN_EPDC_D9 = _MXC_BUILD_GPIO_PIN_MX50(2, 9, 1, 0x1D4, 0x570),
-	MX50_PIN_EPDC_D10 = _MXC_BUILD_GPIO_PIN_MX50(2, 10, 1, 0x1D8, 0x574),
-	MX50_PIN_EPDC_D11 = _MXC_BUILD_GPIO_PIN_MX50(2, 11, 1, 0x1DC, 0x578),
-	MX50_PIN_EPDC_D12 = _MXC_BUILD_GPIO_PIN_MX50(2, 12, 1, 0x1E0, 0x57C),
-	MX50_PIN_EPDC_D13 = _MXC_BUILD_GPIO_PIN_MX50(2, 13, 1, 0x1E4, 0x580),
-	MX50_PIN_EPDC_D14 = _MXC_BUILD_GPIO_PIN_MX50(2, 14, 1, 0x1E8, 0x584),
-	MX50_PIN_EPDC_D15 = _MXC_BUILD_GPIO_PIN_MX50(2, 15, 1, 0x1EC, 0x588),
-	MX50_PIN_EPDC_GDCLK = _MXC_BUILD_GPIO_PIN_MX50(2, 16, 1, 0x1F0, 0x58C),
-	MX50_PIN_EPDC_GDSP = _MXC_BUILD_GPIO_PIN_MX50(2, 17, 1, 0x1F4, 0x590),
-	MX50_PIN_EPDC_GDOE = _MXC_BUILD_GPIO_PIN_MX50(2, 18, 1, 0x1F8, 0x594),
-	MX50_PIN_EPDC_GDRL = _MXC_BUILD_GPIO_PIN_MX50(2, 19, 1, 0x1FC, 0x598),
-	MX50_PIN_EPDC_SDCLK = _MXC_BUILD_GPIO_PIN_MX50(2, 20, 1, 0x200, 0x59C),
-	MX50_PIN_EPDC_SDOEZ = _MXC_BUILD_GPIO_PIN_MX50(2, 21, 1, 0x204, 0x5A0),
-	MX50_PIN_EPDC_SDOED = _MXC_BUILD_GPIO_PIN_MX50(2, 22, 1, 0x208, 0x5A4),
-	MX50_PIN_EPDC_SDOE = _MXC_BUILD_GPIO_PIN_MX50(2, 23, 1, 0x20C, 0x5A8),
-	MX50_PIN_EPDC_SDLE = _MXC_BUILD_GPIO_PIN_MX50(2, 24, 1, 0x210, 0x5AC),
-	MX50_PIN_EPDC_SDCLKN = _MXC_BUILD_GPIO_PIN_MX50(2, 25, 1, 0x214, 0x5B0),
-	MX50_PIN_EPDC_SDSHR = _MXC_BUILD_GPIO_PIN_MX50(2, 26, 1, 0x218, 0x5B4),
-	MX50_PIN_EPDC_PWRCOM = _MXC_BUILD_GPIO_PIN_MX50(2, 27, 1, 0x21C, 0x5B8),
-	MX50_PIN_EPDC_PWRSTAT = _MXC_BUILD_GPIO_PIN_MX50(2, 28, 1, 0x220, 0x5BC),
-	MX50_PIN_EPDC_PWRCTRL0 = _MXC_BUILD_GPIO_PIN_MX50(2, 29, 1, 0x224, 0x5C0),
-	MX50_PIN_EPDC_PWRCTRL1 = _MXC_BUILD_GPIO_PIN_MX50(2, 30, 1, 0x228, 0x5C4),
-	MX50_PIN_EPDC_PWRCTRL2 = _MXC_BUILD_GPIO_PIN_MX50(2, 31, 1, 0x22C, 0x5C8),
-	MX50_PIN_EPDC_PWRCTRL3 = _MXC_BUILD_GPIO_PIN_MX50(3, 20, 1, 0x230, 0x5CC),
-	MX50_PIN_EPDC_VCOM0 = _MXC_BUILD_GPIO_PIN_MX50(3, 21, 1, 0x234, 0x5D0),
-	MX50_PIN_EPDC_VCOM1 = _MXC_BUILD_GPIO_PIN_MX50(3, 22, 1, 0x238, 0x5D4),
-	MX50_PIN_EPDC_BDR0 = _MXC_BUILD_GPIO_PIN_MX50(3, 23, 1, 0x23C, 0x5D8),
-	MX50_PIN_EPDC_BDR1 = _MXC_BUILD_GPIO_PIN_MX50(3, 24, 1, 0x240, 0x5DC),
-	MX50_PIN_EPDC_SDCE0 = _MXC_BUILD_GPIO_PIN_MX50(3, 25, 1, 0x244, 0x5E0),
-	MX50_PIN_EPDC_SDCE1 = _MXC_BUILD_GPIO_PIN_MX50(3, 26, 1, 0x248, 0x5E4),
-	MX50_PIN_EPDC_SDCE2 = _MXC_BUILD_GPIO_PIN_MX50(3, 27, 1, 0x24C, 0x5E8),
-	MX50_PIN_EPDC_SDCE3 = _MXC_BUILD_GPIO_PIN_MX50(3, 28, 1, 0x250, 0x5EC),
-	MX50_PIN_EPDC_SDCE4 = _MXC_BUILD_GPIO_PIN_MX50(3, 29, 1, 0x254, 0x5F0),
-	MX50_PIN_EPDC_SDCE5 = _MXC_BUILD_GPIO_PIN_MX50(3, 30, 1, 0x258, 0x5F4),
-	MX50_PIN_EIM_DA0 = _MXC_BUILD_GPIO_PIN_MX50(0, 0, 1, 0x25C, 0x5F8),
-	MX50_PIN_EIM_DA1 = _MXC_BUILD_GPIO_PIN_MX50(0, 1, 1, 0x260, 0x5FC),
-	MX50_PIN_EIM_DA2 = _MXC_BUILD_GPIO_PIN_MX50(0, 2, 1, 0x264, 0x600),
-	MX50_PIN_EIM_DA3 = _MXC_BUILD_GPIO_PIN_MX50(0, 3, 1, 0x268, 0x604),
-	MX50_PIN_EIM_DA4 = _MXC_BUILD_GPIO_PIN_MX50(0, 4, 1, 0x26C, 0x608),
-	MX50_PIN_EIM_DA5 = _MXC_BUILD_GPIO_PIN_MX50(0, 5, 1, 0x270, 0x60C),
-	MX50_PIN_EIM_DA6 = _MXC_BUILD_GPIO_PIN_MX50(0, 6, 1, 0x274, 0x610),
-	MX50_PIN_EIM_DA7 = _MXC_BUILD_GPIO_PIN_MX50(0, 7, 1, 0x278, 0x614),
-	MX50_PIN_EIM_DA8 = _MXC_BUILD_GPIO_PIN_MX50(0, 8, 1, 0x27C, 0x618),
-	MX50_PIN_EIM_DA9 = _MXC_BUILD_GPIO_PIN_MX50(0, 9, 1, 0x280, 0x61C),
-	MX50_PIN_EIM_DA10 = _MXC_BUILD_GPIO_PIN_MX50(0, 10, 1, 0x284, 0x620),
-	MX50_PIN_EIM_DA11 = _MXC_BUILD_GPIO_PIN_MX50(0, 11, 1, 0x288, 0x624),
-	MX50_PIN_EIM_DA12 = _MXC_BUILD_GPIO_PIN_MX50(0, 12, 1, 0x28C, 0x628),
-	MX50_PIN_EIM_DA13 = _MXC_BUILD_GPIO_PIN_MX50(0, 13, 1, 0x290, 0x62C),
-	MX50_PIN_EIM_DA14 = _MXC_BUILD_GPIO_PIN_MX50(0, 14, 1, 0x294, 0x630),
-	MX50_PIN_EIM_DA15 = _MXC_BUILD_GPIO_PIN_MX50(0, 15, 1, 0x298, 0x634),
-	MX50_PIN_EIM_CS2 = _MXC_BUILD_GPIO_PIN_MX50(0, 16, 1, 0x29C, 0x638),
-	MX50_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN_MX50(0, 17, 1, 0x2A0, 0x63C),
-	MX50_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN_MX50(0, 18, 1, 0x2A4, 0x640),
-	MX50_PIN_EIM_EB0 = _MXC_BUILD_GPIO_PIN_MX50(0, 19, 1, 0x2A8, 0x644),
-	MX50_PIN_EIM_EB1 = _MXC_BUILD_GPIO_PIN_MX50(0, 20, 1, 0x2AC, 0x648),
-	MX50_PIN_EIM_WAIT = _MXC_BUILD_GPIO_PIN_MX50(0, 21, 1, 0x2B0, 0x64C),
-	MX50_PIN_EIM_BCLK = _MXC_BUILD_GPIO_PIN_MX50(0, 22, 1, 0x2B4, 0x650),
-	MX50_PIN_EIM_RDY = _MXC_BUILD_GPIO_PIN_MX50(0, 23, 1, 0x2B8, 0x654),
-	MX50_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN_MX50(0, 24, 1, 0x2BC, 0x658),
-	MX50_PIN_EIM_RW = _MXC_BUILD_GPIO_PIN_MX50(0, 25, 1, 0x2C0, 0x65C),
-	MX50_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN_MX50(0, 26, 1, 0x2C4, 0x660),
-	MX50_PIN_EIM_CRE = _MXC_BUILD_GPIO_PIN_MX50(0, 27, 1, 0x2C8, 0x664),
-
-};
-
-/*!
- * various IOMUX input select register index
- */
-enum iomux_input_select_mx50 {
-	MUX_IN_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0,
-	MUX_IN_AUDMUX_P4_INPUT_DB_AMX_SELECT_I,
-	MUX_IN_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT,
-	MUX_IN_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT,
-	MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT,
-	MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT,
-	MUX_IN_CCM_PLL1_BYPASS_CLK_SELECT_INPUT,
-	MUX_IN_CCM_PLL2_BYPASS_CLK_SELECT_INPUT,
-	MUX_IN_CCM_PLL3_BYPASS_CLK_SELECT_INPUT,
-	MUX_IN_CSPI_IPP_IND_DATAREADY_B_SELECT_INPUT,
-	MUX_IN_CSPI_IPP_IND_SS1_B_SELECT_INPUT,
-	MUX_IN_CSPI_IPP_IND_SS2_B_SELECT_INPUT,
-	MUX_IN_CSPI_IPP_IND_SS3_B_SELECT_INPUT,
-	MUX_IN_ELCDIF_LCDIF_BUSY_SELECT_INPUT,
-	MUX_IN_ELCDIF_LCDIF_RXDATA_0_SELECT_INPUT,
-	MUX_IN_ELCDIF_LCDIF_RXDATA_1_SELECT_INPUT,
-	MUX_IN_ELCDIF_LCDIF_RXDATA_2_SELECT_INPUT,
-	MUX_IN_ELCDIF_LCDIF_RXDATA_3_SELECT_INPUT,
-	MUX_IN_ELCDIF_LCDIF_RXDATA_4_SELECT_INPUT,
-	MUX_IN_ELCDIF_LCDIF_RXDATA_5_SELECT_INPUT,
-	MUX_IN_ELCDIF_LCDIF_RXDATA_6_SELECT_INPUT,
-	MUX_IN_ELCDIF_LCDIF_RXDATA_7_SELECT_INPUT,
-	MUX_IN_ELCDIF_LCDIF_RXDATA_8_SELECT_INPUT,
-	MUX_IN_ELCDIF_LCDIF_RXDATA_9_SELECT_INPUT,
-	MUX_IN_ELCDIF_LCDIF_RXDATA_10_SELECT_INPUT,
-	MUX_IN_ELCDIF_LCDIF_RXDATA_11_SELECT_INPUT,
-	MUX_IN_ELCDIF_LCDIF_RXDATA_12_SELECT_INPUT,
-	MUX_IN_ELCDIF_LCDIF_RXDATA_13_SELECT_INPUT,
-	MUX_IN_ELCDIF_LCDIF_RXDATA_14_SELECT_INPUT,
-	MUX_IN_ELCDIF_LCDIF_RXDATA_15_SELECT_INPUT,
-	MUX_IN_ELCDIF_VSYNC_I_SELECT_INPUT,
-	MUX_IN_ESDHC2_IPP_CARD_DET_SELECT_INPUT,
-	MUX_IN_ESDHC2_IPP_WP_ON_SELECT_INPUT,
-	MUX_IN_ESDHC4_IPP_CARD_CLK_IN_SELECT_INPUT,
-	MUX_IN_ESDHC4_IPP_CMD_IN_SELECT_INPUT,
-	MUX_IN_ESDHC4_IPP_DAT0_IN_SELECT_INPUT,
-	MUX_IN_ESDHC4_IPP_DAT1_IN_SELECT_INPUT,
-	MUX_IN_ESDHC4_IPP_DAT2_IN_SELECT_INPUT,
-	MUX_IN_ESDHC4_IPP_DAT3_IN_SELECT_INPUT,
-	MUX_IN_ESDHC4_IPP_DAT4_IN_SELECT_INPUT,
-	MUX_IN_ESDHC4_IPP_DAT5_IN_SELECT_INPUT,
-	MUX_IN_ESDHC4_IPP_DAT6_IN_SELECT_INPUT,
-	MUX_IN_ESDHC4_IPP_DAT7_IN_SELECT_INPUT,
-	MUX_IN_FEC_FEC_COL_SELECT_INPUT,
-	MUX_IN_FEC_FEC_MDI_SELECT_INPUT,
-	MUX_IN_FEC_FEC_RDATA_0_SELECT_INPUT,
-	MUX_IN_FEC_FEC_RDATA_1_SELECT_INPUT,
-	MUX_IN_FEC_FEC_RX_CLK_SELECT_INPUT,
-	MUX_IN_FEC_FEC_RX_DV_SELECT_INPUT,
-	MUX_IN_FEC_FEC_RX_ER_SELECT_INPUT,
-	MUX_IN_FEC_FEC_TX_CLK_SELECT_INPUT,
-	MUX_IN_KPP_IPP_IND_COL_4_SELECT_INPUT,
-	MUX_IN_KPP_IPP_IND_COL_5_SELECT_INPUT,
-	MUX_IN_KPP_IPP_IND_COL_6_SELECT_INPUT,
-	MUX_IN_KPP_IPP_IND_COL_7_SELECT_INPUT,
-	MUX_IN_KPP_IPP_IND_ROW_4_SELECT_INPUT,
-	MUX_IN_KPP_IPP_IND_ROW_5_SELECT_INPUT,
-	MUX_IN_KPP_IPP_IND_ROW_6_SELECT_INPUT,
-	MUX_IN_KPP_IPP_IND_ROW_7_SELECT_INPUT,
-	MUX_IN_RAWNAND_U_GPMI_INPUT_GPMI_DQS_IN_SELECT_INPUT,
-	MUX_IN_RAWNAND_U_GPMI_INPUT_GPMI_RDY0_IN_SELECT_INPUT,
-	MUX_IN_SDMA_EVENTS_14_SELECT_INPUT,
-	MUX_IN_SDMA_EVENTS_15_SELECT_INPUT,
-	MUX_IN_UART1_IPP_UART_RTS_B_SELECT_INPUT,
-	MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
-	MUX_IN_UART2_IPP_UART_RTS_B_SELECT_INPUT,
-	MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,
-	MUX_IN_UART3_IPP_UART_RTS_B_SELECT_INPUT,
-	MUX_IN_UART3_IPP_UART_RXD_MUX_SELECT_INPUT,
-	MUX_IN_UART4_IPP_UART_RTS_B_SELECT_INPUT,
-	MUX_IN_UART4_IPP_UART_RXD_MUX_SELECT_INPUT,
-	MUX_IN_UART5_IPP_UART_RTS_B_SELECT_INPUT,
-	MUX_IN_UART5_IPP_UART_RXD_MUX_SELECT_INPUT,
-	MUX_IN_USBOH1_IPP_IND_OTG_OC_SELECT_INPUT,
-	MUX_IN_WEIMV2_IPP_IND_READ_DATA_0_SELECT_INPUT,
-	MUX_IN_WEIMV2_IPP_IND_READ_DATA_1_SELECT_INPUT,
-	MUX_IN_WEIMV2_IPP_IND_READ_DATA_2_SELECT_INPUT,
-	MUX_IN_WEIMV2_IPP_IND_READ_DATA_3_SELECT_INPUT,
-	MUX_IN_WEIMV2_IPP_IND_READ_DATA_4_SELECT_INPUT,
-	MUX_IN_WEIMV2_IPP_IND_READ_DATA_5_SELECT_INPUT,
-	MUX_IN_WEIMV2_IPP_IND_READ_DATA_6_SELECT_INPUT,
-	MUX_IN_WEIMV2_IPP_IND_READ_DATA_7_SELECT_INPUT,
-	MUX_IN_WEIMV2_IPP_IND_READ_DATA_8_SELECT_INPUT,
-	MUX_IN_WEIMV2_IPP_IND_READ_DATA_9_SELECT_INPUT,
-	MUX_IN_WEIMV2_IPP_IND_READ_DATA_10_SELECT_INPUT,
-	MUX_IN_WEIMV2_IPP_IND_READ_DATA_11_SELECT_INPUT,
-	MUX_IN_WEIMV2_IPP_IND_READ_DATA_12_SELECT_INPUT,
-	MUX_IN_WEIMV2_IPP_IND_READ_DATA_13_SELECT_INPUT,
-	MUX_IN_WEIMV2_IPP_IND_READ_DATA_14_SELECT_INPUT,
-	MUX_IN_WEIMV2_IPP_IND_READ_DATA_15_SELECT_INPUT,
-
-	MUX_INPUT_NUM_MUX,
-};
-
-#endif				/* __ASSEMBLY__ */
-#endif				/* __ASM_ARCH_MXC_MX50_PINS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx50.h b/arch/arm/plat-mxc/include/mach/iomux-mx50.h
new file mode 100644
index 000000000000..8e4a33cdb703
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx50.h
@@ -0,0 +1,513 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __MACH_IOMUX_MX50_H__
+#define __MACH_IOMUX_MX50_H__
+
+#include <mach/iomux-v3.h>
+
+/*
+ * various IOMUX alternate output functions (1-7)
+ */
+typedef enum iomux_config {
+	IOMUX_CONFIG_ALT0,
+	IOMUX_CONFIG_ALT1,
+	IOMUX_CONFIG_ALT2,
+	IOMUX_CONFIG_ALT3,
+	IOMUX_CONFIG_ALT4,
+	IOMUX_CONFIG_ALT5,
+	IOMUX_CONFIG_ALT6,
+	IOMUX_CONFIG_ALT7,
+	IOMUX_CONFIG_GPIO,	/* added to help user use GPIO mode */
+	IOMUX_CONFIG_SION = 0x1 << 4,	/* LOOPBACK:MUX SION bit */
+} iomux_pin_cfg_t;
+
+#define NON_MUX_I	0x3FF
+#define NON_PAD_I	0x7FF
+
+#define IOMUX_TO_IRQ_V3(pin)		(MXC_GPIO_IRQ_START + pin)
+
+#define MX50_ELCDIF_PAD_CTRL	(PAD_CTL_PKE | PAD_CTL_PUE | \
+					PAD_CTL_DSE_HIGH)
+
+#define MX50_WVGA_PAD_CTRL	(PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH)
+
+#define MX50_SD_PAD_CTRL		(PAD_CTL_DSE_HIGH | \
+					PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST)
+
+#define MX50_SD3_PAD_DAT	(PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
+					PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH)
+#define MX50_SD3_PAD_CMD	(PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
+					PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_HIGH)
+#define MX50_SD3_PAD_CLK	(PAD_CTL_PKE | PAD_CTL_PUE | \
+					PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH)
+#define MX50_UART_PAD_CTRL	(PAD_CTL_DSE_HIGH | PAD_CTL_PKE)
+#define MX50_I2C_PAD_CTRL	(PAD_CTL_ODE | PAD_CTL_DSE_HIGH | \
+					PAD_CTL_PUS_100K_UP | PAD_CTL_HYS)
+#define MX50_USB_PAD_CTRL	(PAD_CTL_PKE | PAD_CTL_PUE | \
+					PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP)
+
+#define MX50_FEC_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
+					PAD_CTL_PUS_22K_UP | PAD_CTL_ODE | \
+					PAD_CTL_DSE_HIGH)
+
+#define MX50_OWIRE_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
+					PAD_CTL_PUS_100K_UP | PAD_CTL_ODE | \
+					PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST)
+
+#define MX50_PAD_KEY_COL0__GPIO_4_0	IOMUX_PAD(0x2CC, 0x20, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_KEY_ROW0__GPIO_4_1	IOMUX_PAD(0x2D0, 0x24, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_KEY_COL1__GPIO_4_2	IOMUX_PAD(0x2D4, 0x28, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_KEY_ROW1__GPIO_4_3	IOMUX_PAD(0x2D8, 0x2C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_KEY_COL2__GPIO_4_4	IOMUX_PAD(0x2DC, 0x30, 1, 0x0, 0, \
+						MX50_SD_PAD_CTRL)
+#define MX50_PAD_KEY_ROW2__GPIO_4_5	IOMUX_PAD(0x2E0, 0x34, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_KEY_COL3__GPIO_4_6	IOMUX_PAD(0x2E4, 0x38, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_KEY_ROW3__GPIO_4_7	IOMUX_PAD(0x2E8, 0x3C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_I2C1_SCL__GPIO_6_18	IOMUX_PAD(0x2EC, 0x40, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_I2C1_SDA__GPIO_6_19	IOMUX_PAD(0x2F0, 0x44, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_I2C2_SCL__GPIO_6_20	IOMUX_PAD(0x2F4, 0x48, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_I2C2_SDA__GPIO_6_21	IOMUX_PAD(0x2F8, 0x4C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_I2C3_SCL__GPIO_6_22	IOMUX_PAD(0x2FC, 0x50, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_I2C3_SDA__GPIO_6_23	IOMUX_PAD(0x300, 0x54, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_PWM1__GPIO_6_24	IOMUX_PAD(0x304, 0x58, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_PWM2__GPIO_6_25	IOMUX_PAD(0x308, 0x5C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_OWIRE__GPIO_6_26	IOMUX_PAD(0x30C, 0x60, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPITO__GPIO_6_27	IOMUX_PAD(0x310, 0x64, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_WDOG__GPIO_6_28	IOMUX_PAD(0x314, 0x68, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SSI_TXFS__GPIO_6_0	IOMUX_PAD(0x318, 0x6C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SSI_TXC__GPIO_6_1	IOMUX_PAD(0x31C, 0x70, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SSI_TXD__GPIO_6_2	IOMUX_PAD(0x320, 0x74, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SSI_RXD__GPIO_6_3	IOMUX_PAD(0x324, 0x78, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SSI_RXFS__GPIO_6_4	IOMUX_PAD(0x328, 0x7C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SSI_RXC__GPIO_6_5	IOMUX_PAD(0x32C, 0x80, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_UART1_TXD__GPIO_6_6	IOMUX_PAD(0x330, 0x84, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_UART1_RXD__GPIO_6_7	IOMUX_PAD(0x334, 0x88, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_UART1_CTS__GPIO_6_8	IOMUX_PAD(0x338, 0x8C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_UART1_RTS__GPIO_6_9	IOMUX_PAD(0x33C, 0x90, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_UART2_TXD__GPIO_6_10	IOMUX_PAD(0x340, 0x94, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_UART2_RXD__GPIO_6_11	IOMUX_PAD(0x344, 0x98, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_UART2_CTS__GPIO_6_12	IOMUX_PAD(0x348, 0x9C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_UART2_RTS__GPIO_6_13	IOMUX_PAD(0x34C, 0xA0, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_UART3_TXD__GPIO_6_14	IOMUX_PAD(0x350, 0xA4, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_UART3_RXD__GPIO_6_15	IOMUX_PAD(0x354, 0xA8, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_UART4_TXD__GPIO_6_16	IOMUX_PAD(0x358, 0xAC, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_UART4_RXD__GPIO_6_17	IOMUX_PAD(0x35C, 0xB0, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_CSPI_SCLK__GPIO_4_8	IOMUX_PAD(0x360, 0xB4, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_CSPI_MOSI__GPIO_4_9	IOMUX_PAD(0x364, 0xB8, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_CSPI_MISO__GPIO_4_10	IOMUX_PAD(0x368, 0xBC, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_CSPI_SS0__GPIO_4_11	IOMUX_PAD(0x36C, 0xC0, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_ECSPI1_SCLK__GPIO_4_12	IOMUX_PAD(0x370, 0xC4, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_ECSPI1_MOSI__GPIO_4_13	IOMUX_PAD(0x374, 0xC8, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_ECSPI1_MISO__GPIO_4_14	IOMUX_PAD(0x378, 0xCC, 1, 0x0, 0, NO_PAD_CTRL)
+
+/* HP detect */
+#define MX50_PAD_ECSPI1_SS0__GPIO_4_15	IOMUX_PAD(0x37C, 0xD0, 1, 0x0, 0, \
+							PAD_CTL_PUS_100K_UP)
+#define MX50_PAD_ECSPI2_SCLK__GPIO_4_16	IOMUX_PAD(0x380, 0xD4, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_ECSPI2_MOSI__GPIO_4_17	IOMUX_PAD(0x384, 0xD8, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_ECSPI2_MISO__GPIO_4_18	IOMUX_PAD(0x388, 0xDC, 1, 0x0, 0, \
+							PAD_CTL_PUS_100K_UP)
+#define MX50_PAD_ECSPI2_SS0__GPIO_4_19	IOMUX_PAD(0x38C, 0xE0, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD1_CLK__GPIO_5_0	IOMUX_PAD(0x390, 0xE4, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD1_CMD__GPIO_5_1	IOMUX_PAD(0x394, 0xE8, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD1_D0__GPIO_5_2	IOMUX_PAD(0x398, 0xEC, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD1_D1__GPIO_5_3	IOMUX_PAD(0x39C, 0xF0, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD1_D2__GPIO_5_4	IOMUX_PAD(0x3A0, 0xF4, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD1_D3__GPIO_5_5	IOMUX_PAD(0x3A4, 0xF8, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD2_CLK__GPIO_5_6	IOMUX_PAD(0x3A8, 0xFC, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD2_CMD__GPIO_5_7	IOMUX_PAD(0x3AC, 0x100, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD2_D0__GPIO_5_8	IOMUX_PAD(0x3B0, 0x104, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD2_D1__GPIO_5_9	IOMUX_PAD(0x3B4, 0x108, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD2_D2__GPIO_5_10	IOMUX_PAD(0x3B8, 0x10C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD2_D3__GPIO_5_11	IOMUX_PAD(0x3BC, 0x110, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD2_D4__GPIO_5_12	IOMUX_PAD(0x3C0, 0x114, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD2_D5__GPIO_5_13	IOMUX_PAD(0x3C4, 0x118, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD2_D6__GPIO_5_14	IOMUX_PAD(0x3C8, 0x11C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD2_D7__GPIO_5_15	IOMUX_PAD(0x3CC, 0x120, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD2_WP__GPIO_5_16	IOMUX_PAD(0x3D0, 0x124, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD2_CD__GPIO_5_17	IOMUX_PAD(0x3D4, 0x128, 1, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_PMIC_ON_REQ__PMIC_ON_REQ	IOMUX_PAD(0x3D8, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_PMIC_STBY_REQ__PMIC_STBY_REQ	IOMUX_PAD(0x3DC, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_PMIC_PORT_B__PMIC_PORT_B	IOMUX_PAD(0x3E0, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_PMIC_BOOT_MODE1__PMIC_BOOT_MODE1	IOMUX_PAD(0x3E4, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_PMIC_RESET_IN_B__PMIC_RESET_IN_B	IOMUX_PAD(0x3E8, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_PMIC_BOOT_MODE0__PMIC_BOOT_MODE0	IOMUX_PAD(0x3EC, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_PMIC_TEST_MODE__PMIC_TEST_MODE	IOMUX_PAD(0x3F0, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_PMIC_JTAG_TMS__PMIC_JTAG_TMS	IOMUX_PAD(0x3F4, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_PMIC_JTAG_MOD__PMIC_JTAG_MOD	IOMUX_PAD(0x3F8, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_PMIC_JTAG_TRSTB__PMIC_JTAG_TRSTB	IOMUX_PAD(0x3FC, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_PMIC_JTAG_TDI__PMIC_JTAG_TDI	IOMUX_PAD(0x400, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_PMIC_JTAG_TCK__PMIC_JTAG_TCK	IOMUX_PAD(0x404, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_PMIC_JTAG_TDO__PMIC_JTAG_TDO	IOMUX_PAD(0x408, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_DISP_D0__GPIO_2_0	IOMUX_PAD(0x40C, 0x12C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D1__GPIO_2_1	IOMUX_PAD(0x410, 0x130, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D2__GPIO_2_2	IOMUX_PAD(0x414, 0x134, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D3__GPIO_2_3	IOMUX_PAD(0x418, 0x138, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D4__GPIO_2_4	IOMUX_PAD(0x41C, 0x13C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D5__GPIO_2_5	IOMUX_PAD(0x420, 0x140, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D6__GPIO_2_6	IOMUX_PAD(0x424, 0x144, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D7__GPIO_2_7	IOMUX_PAD(0x428, 0x148, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_WR__GPIO_2_16	IOMUX_PAD(0x42C, 0x14C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_RD__GPIO_2_19	IOMUX_PAD(0x430, 0x150, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_RS__GPIO_2_17	IOMUX_PAD(0x434, 0x154, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_CS__GPIO_2_21	IOMUX_PAD(0x438, 0x158, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_BUSY__GPIO_2_18	IOMUX_PAD(0x43C, 0x15C, 1, 0x0, 0, \
+						MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_DISP_RESET__GPIO_2_20	IOMUX_PAD(0x440, 0x160, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD3_CMD__GPIO_5_18	IOMUX_PAD(0x444, 0x164, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD3_CLK__GPIO_5_19	IOMUX_PAD(0x448, 0x168, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD3_D0__GPIO_5_20	IOMUX_PAD(0x44C, 0x16C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD3_D1__GPIO_5_21	IOMUX_PAD(0x450, 0x170, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD3_D2__GPIO_5_22	IOMUX_PAD(0x454, 0x174, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD3_D3__GPIO_5_23	IOMUX_PAD(0x458, 0x178, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD3_D4__GPIO_5_24	IOMUX_PAD(0x45C, 0x17C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD3_D5__GPIO_5_25	IOMUX_PAD(0x460, 0x180, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD3_D6__GPIO_5_26	IOMUX_PAD(0x464, 0x184, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD3_D7__GPIO_5_27	IOMUX_PAD(0x468, 0x188, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD3_WP__GPIO_5_28	IOMUX_PAD(0x46C, 0x18C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D8__GPIO_2_8	IOMUX_PAD(0x470, 0x190, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D9__GPIO_2_9	IOMUX_PAD(0x474, 0x194, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D10__GPIO_2_10	IOMUX_PAD(0x478, 0x198, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D11__GPIO_2_11	IOMUX_PAD(0x47C, 0x19C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D12__GPIO_2_12	IOMUX_PAD(0x480, 0x1A0, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D13__GPIO_2_13	IOMUX_PAD(0x484, 0x1A4, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D14__GPIO_2_14	IOMUX_PAD(0x488, 0x1A8, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D15__GPIO_2_15	IOMUX_PAD(0x48C, 0x1AC, 1, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_EPDC_D0__GPIO_3_0	IOMUX_PAD(0x54C, 0x1B0, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D1__GPIO_3_1	IOMUX_PAD(0x550, 0x1B4, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D2__GPIO_3_2	IOMUX_PAD(0x554, 0x1B8, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D3__GPIO_3_3	IOMUX_PAD(0x558, 0x1BC, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D4__GPIO_3_4	IOMUX_PAD(0x55C, 0x1C0, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D5__GPIO_3_5	IOMUX_PAD(0x560, 0x1C4, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D6__GPIO_3_6	IOMUX_PAD(0x564, 0x1C8, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D7__GPIO_3_7	IOMUX_PAD(0x568, 0x1CC, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D8__GPIO_3_8	IOMUX_PAD(0x56C, 0x1D0, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D9__GPIO_3_9	IOMUX_PAD(0x570, 0x1D4, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D10__GPIO_3_10	IOMUX_PAD(0x574, 0x1D8, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D11__GPIO_3_11	IOMUX_PAD(0x578, 0x1DC, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D12__GPIO_3_12	IOMUX_PAD(0x57C, 0x1E0, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D13__GPIO_3_13	IOMUX_PAD(0x580, 0x1E4, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D14__GPIO_3_14	IOMUX_PAD(0x584, 0x1E8, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D15__GPIO_3_15	IOMUX_PAD(0x588, 0x1EC, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_GDCLK__GPIO_3_16	IOMUX_PAD(0x58C, 0x1F0, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_GDSP__GPIO_3_17	IOMUX_PAD(0x590, 0x1F4, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_GDOE__GPIO_3_18	IOMUX_PAD(0x594, 0x1F8, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_GDRL__GPIO_3_19	IOMUX_PAD(0x598, 0x1FC, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDCLK__GPIO_3_20	IOMUX_PAD(0x59C, 0x200, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDOEZ__GPIO_3_21	IOMUX_PAD(0x5A0, 0x204, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDOED__GPIO_3_22	IOMUX_PAD(0x5A4, 0x208, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDOE__GPIO_3_23	IOMUX_PAD(0x5A8, 0x20C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDLE__GPIO_3_24	IOMUX_PAD(0x5AC, 0x210, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDCLKN__GPIO_3_25	IOMUX_PAD(0x5B0, 0x214, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDSHR__GPIO_3_26	IOMUX_PAD(0x5B4, 0x218, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_PWRCOM__GPIO_3_27	IOMUX_PAD(0x5B8, 0x21C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_PWRSTAT__GPIO_3_28	IOMUX_PAD(0x5BC, 0x220, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_PWRCTRL0__GPIO_3_29	IOMUX_PAD(0x5C0, 0x224, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_PWRCTRL1__GPIO_3_30	IOMUX_PAD(0x5C4, 0x228, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_PWRCTRL2__GPIO_3_31	IOMUX_PAD(0x5C8, 0x22C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_PWRCTRL3__GPIO_4_20	IOMUX_PAD(0x5CC, 0x230, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_VCOM0__GPIO_4_21	IOMUX_PAD(0x5D0, 0x234, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_VCOM1__GPIO_4_22	IOMUX_PAD(0x5D4, 0x238, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_BDR0__GPIO_4_23	IOMUX_PAD(0x5D8, 0x23C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_BDR1__GPIO_4_24	IOMUX_PAD(0x5DC, 0x240, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDCE0__GPIO_4_25	IOMUX_PAD(0x5E0, 0x244, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDCE1__GPIO_4_26	IOMUX_PAD(0x5E4, 0x248, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDCE2__GPIO_4_27	IOMUX_PAD(0x5E8, 0x24C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDCE3__GPIO_4_28	IOMUX_PAD(0x5EC, 0x250, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDCE4__GPIO_4_29	IOMUX_PAD(0x5F0, 0x254, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDCE5__GPIO_4_30	IOMUX_PAD(0x5F4, 0x258, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_DA0__GPIO_1_0	IOMUX_PAD(0x5F8, 0x25C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_DA1__GPIO_1_1	IOMUX_PAD(0x5FC, 0x260, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_DA2__GPIO_1_2	IOMUX_PAD(0x600, 0x264, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_DA3__GPIO_1_3	IOMUX_PAD(0x604, 0x268, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_DA4__GPIO_1_4	IOMUX_PAD(0x608, 0x26C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_DA5__GPIO_1_5	IOMUX_PAD(0x60C, 0x270, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_DA6__GPIO_1_6	IOMUX_PAD(0x610, 0x274, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_DA7__GPIO_1_7	IOMUX_PAD(0x614, 0x278, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_DA8__GPIO_1_8	IOMUX_PAD(0x618, 0x27C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_DA9__GPIO_1_9	IOMUX_PAD(0x61C, 0x280, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_DA10__GPIO_1_10	IOMUX_PAD(0x620, 0x284, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_DA11__GPIO_1_11	IOMUX_PAD(0x624, 0x288, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_DA12__GPIO_1_12	IOMUX_PAD(0x628, 0x28C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_DA13__GPIO_1_13	IOMUX_PAD(0x62C, 0x290, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_DA14__GPIO_1_14	IOMUX_PAD(0x630, 0x294, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_DA15__GPIO_1_15	IOMUX_PAD(0x634, 0x298, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_CS2__GPIO_1_16	IOMUX_PAD(0x638, 0x29C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_CS1__GPIO_1_17	IOMUX_PAD(0x63C, 0x2A0, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_CS0__GPIO_1_18	IOMUX_PAD(0x640, 0x2A4, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_EB0__GPIO_1_19	IOMUX_PAD(0x644, 0x2A8, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_EB1__GPIO_1_20	IOMUX_PAD(0x648, 0x2AC, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_WAIT__GPIO_1_21	IOMUX_PAD(0x64C, 0x2B0, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_BCLK__GPIO_1_22	IOMUX_PAD(0x650, 0x2B4, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_RDY__GPIO_1_23	IOMUX_PAD(0x654, 0x2B8, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_OE__GPIO_1_24	IOMUX_PAD(0x658, 0x2BC, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_RW__GPIO_1_25	IOMUX_PAD(0x65C, 0x2C0, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_LBA__GPIO_1_26	IOMUX_PAD(0x660, 0x2C4, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_CRE__GPIO_1_27	IOMUX_PAD(0x664, 0x2C8, 1, 0x0, 0, NO_PAD_CTRL)
+
+
+/* SD1 */
+#define MX50_PAD_SD1_CMD__SD1_CMD	IOMUX_PAD(0x394, 0xE8, \
+					IOMUX_CONFIG_SION, 0x0, 0, \
+					MX50_SD_PAD_CTRL)
+#define MX50_PAD_SD1_CLK__SD1_CLK	IOMUX_PAD(0x390, 0xE4, \
+					IOMUX_CONFIG_SION, 0x0, 0, \
+					MX50_SD_PAD_CTRL)
+#define MX50_PAD_SD1_D0__SD1_D0	IOMUX_PAD(0x398, 0xEC, 0, 0x0, 0, \
+						MX50_SD_PAD_CTRL)
+#define MX50_PAD_SD1_D1__SD1_D1	IOMUX_PAD(0x39C, 0xF0, 0, 0x0, 0, \
+						MX50_SD_PAD_CTRL)
+#define MX50_PAD_SD1_D2__SD1_D2	IOMUX_PAD(0x3A0, 0xF4, 0, 0x0, 0, \
+						MX50_SD_PAD_CTRL)
+#define MX50_PAD_SD1_D3__SD1_D3	IOMUX_PAD(0x3A4, 0xF8, 0, 0x0, 0, \
+						MX50_SD_PAD_CTRL)
+
+/* SD2 */
+#define MX50_PAD_SD2_CLK__SD2_CLK	IOMUX_PAD(0x3A8, 0xFC, \
+						IOMUX_CONFIG_SION, 0x0, 0, \
+						MX50_SD_PAD_CTRL)
+#define MX50_PAD_SD2_CMD__SD2_CMD	IOMUX_PAD(0x3AC, 0x100, \
+						IOMUX_CONFIG_SION, 0x0, 0, \
+						MX50_SD_PAD_CTRL)
+#define MX50_PAD_SD2_D0__SD2_D0	IOMUX_PAD(0x3B0, 0x104, 0, 0x0, 0, \
+						MX50_SD_PAD_CTRL)
+#define MX50_PAD_SD2_D1__SD2_D1	IOMUX_PAD(0x3B4, 0x108, 0, 0x0, 0, \
+						MX50_SD_PAD_CTRL)
+#define MX50_PAD_SD2_D2__SD2_D2	IOMUX_PAD(0x3B8, 0x10C, 0, 0x0, 0, \
+						MX50_SD_PAD_CTRL)
+#define MX50_PAD_SD2_D3__SD2_D3	IOMUX_PAD(0x3BC, 0x110, 0, 0x0, 0, \
+						MX50_SD_PAD_CTRL)
+#define MX50_PAD_SD2_D4__SD2_D4	IOMUX_PAD(0x3C0, 0x114, 0, 0x0, 0, \
+						MX50_SD_PAD_CTRL)
+#define MX50_PAD_SD2_D5__SD2_D5	IOMUX_PAD(0x3C4, 0x118, 0, 0x0, 0, \
+						MX50_SD_PAD_CTRL)
+#define MX50_PAD_SD2_D6__SD2_D6	IOMUX_PAD(0x3C8, 0x11C, 0, 0x0, 0, \
+						MX50_SD_PAD_CTRL)
+#define MX50_PAD_SD2_D7__SD2_D7	IOMUX_PAD(0x3CC, 0x120, 0, 0x0, 0, \
+						MX50_SD_PAD_CTRL)
+
+/* SD3 */
+#define MX50_PAD_SD3_CMD__SD3_CMD	IOMUX_PAD(0x444, 0x164, 0, 0x0, 0, \
+						MX50_SD3_PAD_CMD)
+#define MX50_PAD_SD3_CLK__SD3_CLK	IOMUX_PAD(0x448, 0x168, 0, 0x0, 0, \
+						MX50_SD3_PAD_CLK)
+#define MX50_PAD_SD3_D0__SD3_D0	IOMUX_PAD(0x44C, 0x16C, 0, 0x0, 0, \
+						MX50_SD3_PAD_DAT)
+#define MX50_PAD_SD3_D1__SD3_D1	IOMUX_PAD(0x450, 0x170, 0, 0x0, 0, \
+						MX50_SD3_PAD_DAT)
+#define MX50_PAD_SD3_D2__SD3_D2	IOMUX_PAD(0x454, 0x174, 0, 0x0, 0, \
+						MX50_SD3_PAD_DAT)
+#define MX50_PAD_SD3_D3__SD3_D3	IOMUX_PAD(0x458, 0x178, 0, 0x0, 0, \
+						MX50_SD3_PAD_DAT)
+#define MX50_PAD_SD3_D4__SD3_D4	IOMUX_PAD(0x45C, 0x17C, 0, 0x0, 0, \
+						MX50_SD3_PAD_DAT)
+#define MX50_PAD_SD3_D5__SD3_D5	IOMUX_PAD(0x460, 0x180, 0, 0x0, 0, \
+						MX50_SD3_PAD_DAT)
+#define MX50_PAD_SD3_D6__SD3_D6	IOMUX_PAD(0x464, 0x184, 0, 0x0, 0, \
+						MX50_SD3_PAD_DAT)
+#define MX50_PAD_SD3_D7__SD3_D7	IOMUX_PAD(0x468, 0x188, 0, 0x0, 0, \
+						MX50_SD3_PAD_DAT)
+
+/* OWIRE */
+#define MX50_PAD_OWIRE__OWIRE	IOMUX_PAD(0x30C, 0x60, 0, 0x0, 0, \
+						MX50_OWIRE_PAD_CTRL)
+
+/* SSI */
+#define MX50_PAD_SSI_TXFS__SSI_TXFS	IOMUX_PAD(0x318, 0x6C, 0, 0x0, 0, \
+						NO_PAD_CTRL)
+#define MX50_PAD_SSI_TXC__SSI_TXC	IOMUX_PAD(0x31C, 0x70, 0, 0x0, 0, \
+						NO_PAD_CTRL)
+#define MX50_PAD_SSI_TXD__SSI_TXD	IOMUX_PAD(0x320, 0x74, 0, 0x0, 0, \
+						NO_PAD_CTRL)
+#define MX50_PAD_SSI_RXD__SSI_RXD	IOMUX_PAD(0x324, 0x78, 0, 0x0, 0, \
+						NO_PAD_CTRL)
+
+/* UART1 and UART2 */
+#define MX50_PAD_UART1_TXD__UART1_TXD	IOMUX_PAD(0x330, 0x84, 0, 0x0, 0, \
+						MX50_UART_PAD_CTRL)
+#define MX50_PAD_UART1_RXD__UART1_RXD	IOMUX_PAD(0x334, 0x88, 0, 0x7c4, 1, \
+						MX50_UART_PAD_CTRL)
+#define MX50_PAD_UART1_CTS__UART1_CTS	IOMUX_PAD(0x338, 0x8C, 0, 0x0, 0, \
+						MX50_UART_PAD_CTRL)
+#define MX50_PAD_UART1_RTS__UART1_RTS	IOMUX_PAD(0x33C, 0x90, 0, 0x7c0, 1, \
+						MX50_UART_PAD_CTRL)
+#define MX50_PAD_UART2_TXD__UART2_TXD	IOMUX_PAD(0x340, 0x94, 0, 0x0, 0, \
+						MX50_UART_PAD_CTRL)
+#define MX50_PAD_UART2_RXD__UART2_RXD	IOMUX_PAD(0x344, 0x98, 0, 0x7cc, 3, \
+						MX50_UART_PAD_CTRL)
+#define MX50_PAD_UART2_CTS__UART2_CTS	IOMUX_PAD(0x348, 0x9C, 0, 0x0, 0, \
+						MX50_UART_PAD_CTRL)
+#define MX50_PAD_UART2_RTS__UART2_RTS	IOMUX_PAD(0x34C, 0xA0, 0, 0x7c8, 3, \
+						MX50_UART_PAD_CTRL)
+
+/* I2C1, I2C2, I2C3 */
+#define MX50_PAD_I2C1_SCL__I2C1_SCL	IOMUX_PAD(0x2EC, 0x40, \
+						IOMUX_CONFIG_SION, 0x0, 0, \
+						MX50_I2C_PAD_CTRL)
+#define MX50_PAD_I2C1_SDA__I2C1_SDA	IOMUX_PAD(0x2F0, 0x44, \
+						IOMUX_CONFIG_SION, 0x0, 0, \
+						MX50_I2C_PAD_CTRL)
+#define MX50_PAD_I2C2_SCL__I2C2_SCL	IOMUX_PAD(0x2F4, 0x48, \
+						IOMUX_CONFIG_SION, 0x0, 0, \
+						MX50_I2C_PAD_CTRL)
+#define MX50_PAD_I2C2_SDA__I2C2_SDA	IOMUX_PAD(0x2F8, 0x4C, \
+						IOMUX_CONFIG_SION, 0x0, 0, \
+						MX50_I2C_PAD_CTRL)
+#define MX50_PAD_I2C3_SCL__I2C3_SCL	IOMUX_PAD(0x2FC, 0x50, \
+						IOMUX_CONFIG_SION, 0x0, 0, \
+						MX50_I2C_PAD_CTRL)
+#define MX50_PAD_I2C3_SDA__I2C3_SDA	IOMUX_PAD(0x300, 0x54, \
+						IOMUX_CONFIG_SION, 0x0, 0, \
+						MX50_I2C_PAD_CTRL)
+
+/* EPDC */
+#define MX50_PAD_EPDC_D0__EPDC_D0	IOMUX_PAD(0x54C, 0x1B0, 0, 0x0, 0, \
+						NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D1__EPDC_D1	IOMUX_PAD(0x550, 0x1B4, 0, 0x0, 0, \
+						NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D2__EPDC_D2	IOMUX_PAD(0x554, 0x1B8, 0, 0x0, 0, \
+						NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D3__EPDC_D3	IOMUX_PAD(0x558, 0x1BC, 0, 0x0, 0, \
+						NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D4__EPDC_D4	IOMUX_PAD(0x55C, 0x1C0, 0, 0x0, 0, \
+						NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D5__EPDC_D5	IOMUX_PAD(0x560, 0x1C4, 0, 0x0, 0, \
+						NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D6__EPDC_D6	IOMUX_PAD(0x564, 0x1C8, 0, 0x0, 0, \
+						NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D7__EPDC_D7	IOMUX_PAD(0x568, 0x1CC, 0, 0x0, 0, \
+						NO_PAD_CTRL)
+#define MX50_PAD_EPDC_GDCLK__EPDC_GDCLK	IOMUX_PAD(0x58C, 0x1F0, 0, 0x0, 0, \
+							NO_PAD_CTRL)
+#define MX50_PAD_EPDC_GDSP__EPDC_GDSP	IOMUX_PAD(0x590, 0x1F4, 0, 0x0, 0, \
+							NO_PAD_CTRL)
+#define MX50_PAD_EPDC_GDOE__EPDC_GDOE	IOMUX_PAD(0x594, 0x1F8, 0, 0x0, 0, \
+							NO_PAD_CTRL)
+#define MX50_PAD_EPDC_GDRL__EPDC_GDRL	IOMUX_PAD(0x598, 0x1FC, 0, 0x0, 0, \
+							NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDCLK__EPDC_SDCLK	IOMUX_PAD(0x59C, 0x200, 0, 0x0, 0, \
+							NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDOE__EPDC_SDOE	IOMUX_PAD(0x5A8, 0x20C, 0, 0x0, 0, \
+							NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDLE__EPDC_SDLE	IOMUX_PAD(0x5AC, 0x210, 0, 0x0, 0, \
+							NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDSHR__EPDC_SDSHR	IOMUX_PAD(0x5B4, 0x218, 0, 0x0, 0, \
+							NO_PAD_CTRL)
+#define MX50_PAD_EPDC_BDR0__EPDC_BDR0	IOMUX_PAD(0x5D8, 0x23C, 0, 0x0, 0, \
+							NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDCE0__EPDC_SDCE0	IOMUX_PAD(0x5E0, 0x244, 0, 0x0, 0, \
+							NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDCE1__EPDC_SDCE1	IOMUX_PAD(0x5E4, 0x248, 0, 0x0, 0, \
+							NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDCE2__EPDC_SDCE2	IOMUX_PAD(0x5E8, 0x24C, 0, 0x0, 0, \
+							NO_PAD_CTRL)
+#define MX50_PAD_DISP_D8__DISP_D8	IOMUX_PAD(0x470, 0x190, 0, \
+					0x0, 0, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_DISP_D9__DISP_D9	IOMUX_PAD(0x474, 0x194, 0, 0x0, 0, \
+						MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_DISP_D10__DISP_D10	IOMUX_PAD(0x478, 0x198, 0, 0x0, 0, \
+						MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_DISP_D11__DISP_D11	IOMUX_PAD(0x47C, 0x19C, 0, 0x0, 0, \
+						MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_DISP_D12__DISP_D12	IOMUX_PAD(0x480, 0x1A0, 0, 0x0, 0, \
+						MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_DISP_D13__DISP_D13	IOMUX_PAD(0x484, 0x1A4, 0, 0x0, 0, \
+						MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_DISP_D14__DISP_D14	IOMUX_PAD(0x488, 0x1A8, 0, 0x0, 0, \
+						MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_DISP_D15__DISP_D15	IOMUX_PAD(0x48C, 0x1AC, 0, 0x0, 0, \
+						MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_DISP_RS__ELCDIF_VSYNC	IOMUX_PAD(0x434, 0x154, 2, 0x0, 0, \
+						MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_DISP_CS__ELCDIF_HSYNC	IOMUX_PAD(0x438, 0x158, 2, 0x0, 0, \
+						MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_DISP_RD__ELCDIF_EN	IOMUX_PAD(0x430, 0x150, 2, 0x0, 0, \
+						MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_DISP_WR__ELCDIF_PIXCLK	IOMUX_PAD(0x42C, 0x14C, 2, 0x0, 0, \
+						MX50_ELCDIF_PAD_CTRL)
+
+/* USB */
+#define MX50_PAD_EPITO__USBH1_PWR	IOMUX_PAD(0x310, 0x64, 2, 0x0, 0, \
+						PAD_CTL_PKE | PAD_CTL_DSE_HIGH)
+#define MX50_PAD_OWIRE__USBH1_OC	IOMUX_PAD(0x30C, 0x60, 2, 0x0, 0, \
+						MX50_USB_PAD_CTRL)
+#define MX50_PAD_PWM2__USBOTG_PWR	IOMUX_PAD(0x308, 0x5C, 2, 0x0, 0, \
+						PAD_CTL_PKE | PAD_CTL_DSE_HIGH)
+#define MX50_PAD_PWM1__USBOTG_OC	IOMUX_PAD(0x304, 0x58, 2, 0x7E8, 1, \
+						MX50_USB_PAD_CTRL)
+
+/* FEC */
+#define MX50_PAD_SSI_RXC__FEC_MDIO	IOMUX_PAD(0x32C, 0x80, 6, 0x774, 1, \
+						MX50_FEC_PAD_CTRL)
+#define MX50_PAD_DISP_D0__FEC_TXCLK	IOMUX_PAD(0x40C, 0x12C, 2, 0x0, 0, \
+						PAD_CTL_HYS | PAD_CTL_PKE)
+#define MX50_PAD_DISP_D1__FEC_RX_ER	IOMUX_PAD(0x410, 0x130, 2, 0x788, 0, \
+						PAD_CTL_HYS | PAD_CTL_PKE)
+#define MX50_PAD_DISP_D2__FEC_RX_DV	IOMUX_PAD(0x414, 0x134, 2, 0x784, 0, \
+						PAD_CTL_HYS | PAD_CTL_PKE)
+#define MX50_PAD_DISP_D3__FEC_RXD1	IOMUX_PAD(0x418, 0x138, 2, 0x77C, 0, \
+						PAD_CTL_HYS | PAD_CTL_PKE)
+#define MX50_PAD_DISP_D4__FEC_RXD0	IOMUX_PAD(0x41C, 0x13C, 2, 0x778, 0, \
+						PAD_CTL_HYS | PAD_CTL_PKE)
+#define MX50_PAD_DISP_D5__FEC_TX_EN	IOMUX_PAD(0x420, 0x140, 2, 0x0, 0, \
+						PAD_CTL_DSE_HIGH)
+#define MX50_PAD_DISP_D6__FEC_TXD1	IOMUX_PAD(0x424, 0x144, 2, 0x0, 0, \
+						PAD_CTL_DSE_HIGH)
+#define MX50_PAD_DISP_D7__FEC_TXD0	IOMUX_PAD(0x428, 0x148, 2, 0x0, 0, \
+						PAD_CTL_DSE_HIGH)
+#define MX50_PAD_SSI_RXFS__FEC_MDC	IOMUX_PAD(0x328, 0x7C, 6, 0x0, 0, \
+						PAD_CTL_DSE_HIGH)
+
+/* WVGA */
+#define MX50_PAD_DISP_D0__DISP_D0	IOMUX_PAD(0x40C, 0x12C, 0, 0x0, 0, \
+						MX50_WVGA_PAD_CTRL)
+#define MX50_PAD_DISP_D1__DISP_D1	IOMUX_PAD(0x410, 0x130, 0, 0x0, 0, \
+						MX50_WVGA_PAD_CTRL)
+#define MX50_PAD_DISP_D2__DISP_D2	IOMUX_PAD(0x414, 0x134, 0, 0x0, 0, \
+						MX50_WVGA_PAD_CTRL)
+#define MX50_PAD_DISP_D3__DISP_D3	IOMUX_PAD(0x418, 0x138, 0, 0x0, 0, \
+						MX50_WVGA_PAD_CTRL)
+#define MX50_PAD_DISP_D4__DISP_D4	IOMUX_PAD(0x41C, 0x13C, 0, 0x0, 0, \
+						MX50_WVGA_PAD_CTRL)
+#define MX50_PAD_DISP_D5__DISP_D5	IOMUX_PAD(0x420, 0x140, 0, 0x0, 0, \
+						MX50_WVGA_PAD_CTRL)
+#define MX50_PAD_DISP_D6__DISP_D6	IOMUX_PAD(0x424, 0x144, 0, 0x0, 0, \
+						MX50_WVGA_PAD_CTRL)
+#define MX50_PAD_DISP_D7__DISP_D7	IOMUX_PAD(0x428, 0x148, 0, 0x0, 0, \
+						MX50_WVGA_PAD_CTRL)
+
+/* CSPI */
+#define MX50_PAD_CSPI_SS0__CSPI_SS0	IOMUX_PAD(0x36C, 0xC0, 0, 0x0, 0, \
+						PAD_CTL_PKE | PAD_CTL_PUE | \
+						PAD_CTL_DSE_HIGH)
+#define MX50_PAD_ECSPI1_MOSI__CSPI_SS1	IOMUX_PAD(0x374, 0xC8, 2, 0x0, 0, \
+						PAD_CTL_PKE | PAD_CTL_PUE | \
+						PAD_CTL_PUS_22K_UP | \
+						PAD_CTL_DSE_HIGH)
+#define MX50_PAD_CSPI_MOSI__CSPI_MOSI	IOMUX_PAD(0x364, 0xB8, 0, 0x0, 0, \
+						NO_PAD_CTRL)
+#define MX50_PAD_CSPI_MISO__CSPI_MISO	IOMUX_PAD(0x368, 0xBC, 0, 0x0, 0, \
+						NO_PAD_CTRL)
+
+
+#endif /* __MACH_IOMUX_MX53_H__ */
+
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h
index 1deda0184892..f2f73d31d5ba 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h
@@ -81,11 +81,13 @@ struct pad_desc {
 
 #define PAD_CTL_ODE			(1 << 3)
 
-#define PAD_CTL_DSE_STANDARD		(0 << 1)
-#define PAD_CTL_DSE_HIGH		(1 << 1)
-#define PAD_CTL_DSE_MAX			(2 << 1)
+#define PAD_CTL_DSE_LOW			(0 << 1)
+#define PAD_CTL_DSE_MED			(1 << 1)
+#define PAD_CTL_DSE_HIGH		(2 << 1)
+#define PAD_CTL_DSE_MAX			(3 << 1)
 
 #define PAD_CTL_SRE_FAST		(1 << 0)
+#define PAD_CTL_SRE_SLOW		(0 << 0)
 
 /*
  * setups a single pad in the iomuxer