diff options
| author | Fabio Estevam <fabio.estevam@freescale.com> | 2014-09-18 20:23:48 -0300 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@linaro.org> | 2014-11-19 11:57:36 +0800 |
| commit | 20f5c504ae136a1bee9e7b170f08bb38159077d2 (patch) | |
| tree | dc6f70754eb589f91e2b2cb0de543de4f9167c89 | |
| parent | dc7aaa041842eb40be7ad7bde0a7e37ac1efd79c (diff) | |
ARM: dts: imx53: Improve SSI clocks description
SSI block has 'ipg' clock for internal peripheral access and also 'baud' clock
for generating bit clock when SSI operates in master mode.
Add the extra 'baud' clock so that we can have SSI functional in master mode.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
| -rw-r--r-- | arch/arm/boot/dts/imx53.dtsi | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index f91725b2e8ab..2a5012a5202e 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -227,7 +227,9 @@ "fsl,imx21-ssi"; reg = <0x50014000 0x4000>; interrupts = <30>; - clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>; + clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>, + <&clks IMX5_CLK_SSI2_ROOT_GATE>; + clock-names = "ipg", "baud"; dmas = <&sdma 24 1 0>, <&sdma 25 1 0>; dma-names = "rx", "tx"; @@ -675,7 +677,9 @@ "fsl,imx21-ssi"; reg = <0x63fcc000 0x4000>; interrupts = <29>; - clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>; + clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>, + <&clks IMX5_CLK_SSI1_ROOT_GATE>; + clock-names = "ipg", "baud"; dmas = <&sdma 28 0 0>, <&sdma 29 0 0>; dma-names = "rx", "tx"; @@ -703,7 +707,9 @@ "fsl,imx21-ssi"; reg = <0x63fe8000 0x4000>; interrupts = <96>; - clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>; + clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>, + <&clks IMX5_CLK_SSI3_ROOT_GATE>; + clock-names = "ipg", "baud"; dmas = <&sdma 46 0 0>, <&sdma 47 0 0>; dma-names = "rx", "tx"; |