diff options
| author | Alexander Shiyan <shc_work@mail.ru> | 2013-12-07 12:26:35 +0400 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@linaro.org> | 2014-02-09 21:33:24 +0800 |
| commit | f4bdf215640f73415ff4e2b3e6b48ae2bdb2636f (patch) | |
| tree | c681569986fdbf33b4b5f0cd9c1dd6ca30f24309 | |
| parent | 40dde68196b5d96ceaffea11552c5f108face3fd (diff) | |
ARM: dts: imx27-phytec-phycore-som: Add pinctrl for CSPI1 and GPIOs used on module
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| -rw-r--r-- | arch/arm/boot/dts/imx27-phytec-phycore-som.dts | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dts b/arch/arm/boot/dts/imx27-phytec-phycore-som.dts index dd26e1588a58..ab75b721bf39 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dts +++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dts @@ -51,6 +51,8 @@ }; &cspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cspi1>; fsl,spi-num-chipselects = <1>; cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; status = "okay"; @@ -181,6 +183,16 @@ &iomuxc { imx27_phycore_som { + pinctrl_cspi1: cspi1grp { + fsl,pins = < + MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0 + MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0 + MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0 + MX27_PAD_CSPI1_SS0__GPIO4_28 0x0 /* SPI1 CS0 */ + MX27_PAD_USB_PWR__GPIO2_23 0x0 /* PMIC IRQ */ + >; + }; + pinctrl_fec1: fec1grp { fsl,pins = < MX27_PAD_SD3_CMD__FEC_TXD0 0x0 |