diff options
| author | Ranjani Vaidyanathan <ra5478@freescale.com> | 2012-09-01 21:31:02 -0500 |
|---|---|---|
| committer | Ranjani Vaidyanathan <ra5478@freescale.com> | 2012-09-03 00:15:52 -0500 |
| commit | d81da79b27f8205c915b9ab78972742964e6436a (patch) | |
| tree | 43f980929829fad4bc18a34b699f18e91fb020a5 | |
| parent | f28276c1190e967ae00f1db53a58a431f15ea368 (diff) | |
ENGR00222835 MX6x-Fix incorrect enabling/disabling of PLL1
PLL1 was enabled without incrementing the usecount, and was
thus not getting disabled under certain conditions.
This causes 2 issues:
1. Increases the power.
2. Causes crashes on MX6SL in audio mode as ARM is switched
to PLL1 assuming its in bypass when entering WAIT mode. But PLL1
is enabled and not in bypass state.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
| -rw-r--r-- | arch/arm/mach-mx6/clock.c | 3 | ||||
| -rwxr-xr-x | arch/arm/mach-mx6/clock_mx6sl.c | 3 |
2 files changed, 0 insertions, 6 deletions
diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c index 8b75aee78964..a3dc7e4aeb1e 100644 --- a/arch/arm/mach-mx6/clock.c +++ b/arch/arm/mach-mx6/clock.c @@ -1334,9 +1334,6 @@ static int _clk_arm_set_rate(struct clk *clk, unsigned long rate) spin_unlock_irqrestore(&clk_lock, flags); return -1; } - /* Need PLL1-MAIN to be ON to write to ARM-PODF bit. */ - if (!pll1_enabled) - pll1_sys_main_clk.enable(&pll1_sys_main_clk); cur_arm_podf = div; diff --git a/arch/arm/mach-mx6/clock_mx6sl.c b/arch/arm/mach-mx6/clock_mx6sl.c index 6bd818ae7139..08212c3c3ecb 100755 --- a/arch/arm/mach-mx6/clock_mx6sl.c +++ b/arch/arm/mach-mx6/clock_mx6sl.c @@ -1239,9 +1239,6 @@ static int _clk_arm_set_rate(struct clk *clk, unsigned long rate) return -1; } - if (!pll1_enabled) - pll1_sys_main_clk.enable(&pll1_sys_main_clk); - cur_arm_podf = div; __raw_writel(div - 1, MXC_CCM_CACRR); |