diff options
| author | Fabio Estevam <fabio.estevam@freescale.com> | 2013-10-29 19:42:22 -0200 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2013-10-29 17:03:40 -0700 |
| commit | f0ac9bebf19001f38afbb93e2dc719a15dfb75e5 (patch) | |
| tree | 61a06d0e6c185c595f3c885fba305bf02464d9ba | |
| parent | 0e51fc360f32b3c025e68ad90cd19d3ec8a0dcc6 (diff) | |
imx-drm: ipuv3-crtc: Invert IPU DI0 clock polarity
sig_cfg.clk_pol controls the 'di0_polarity_disp_clk' bit of register
IPUx_DI0_GENERAL through the following code in imx-drm/ipu-v3/ipu-di.c:
if (!sig->clk_pol)
di_gen |= DI_GEN_POLARITY_DISP_CLK;
With 'di0_polarity_disp_clk' bit set we do not have stable HDMI output on
mx6solo: contours of pictures look jittery and the white colour does not appear
really white.
Russell King initially reported this problem at:
http://www.spinics.net/lists/arm-kernel/msg279805.html
Inverting 'di0_polarity_disp_clk' leads to stable HDMI output image.
Tested on the following boards:
- mx6solowandboard (HDMI output)
- mx6qwandboard (HDMI output)
- mx6qsabrelite (LVDS)
- mx6qsabresd (HDMI output and LVDS)
- mx6dlsabresd (HDMI output)
- mx53qsb (parallel WVGA display)
Reported-by: Russell King <rmk+kernel@arm.linux.org.uk>
Suggested-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| -rw-r--r-- | drivers/staging/imx-drm/ipuv3-crtc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/staging/imx-drm/ipuv3-crtc.c b/drivers/staging/imx-drm/ipuv3-crtc.c index f1112dfa6bf6..670a56a834f1 100644 --- a/drivers/staging/imx-drm/ipuv3-crtc.c +++ b/drivers/staging/imx-drm/ipuv3-crtc.c @@ -157,7 +157,7 @@ static int ipu_crtc_mode_set(struct drm_crtc *crtc, sig_cfg.Vsync_pol = 1; sig_cfg.enable_pol = 1; - sig_cfg.clk_pol = 0; + sig_cfg.clk_pol = 1; sig_cfg.width = mode->hdisplay; sig_cfg.height = mode->vdisplay; sig_cfg.pixel_fmt = out_pixel_fmt; |