diff options
| author | Martin Chi <mchi@nvidia.com> | 2014-02-11 21:53:17 +0800 |
|---|---|---|
| committer | Martin Chi <mchi@nvidia.com> | 2014-02-13 00:17:11 -0800 |
| commit | 2691a4b4f201e7d8200ece25b1be04de3e35c608 (patch) | |
| tree | e27985fbece757ff593559cf360fe2053e3f7ace | |
| parent | 53090b82da773d0b5076755813ca86ddc8999c69 (diff) | |
Enable UHSIC bus keepers always
Currently bus keepers are enabled 1 clock later
after drivers are tristated. But to be on safer
side bus keepers are enabled always.
Bug 1032043
Bug 1451863
Change-Id: I5a696c5fba1dde161fc674d80e3b4b2e937348fd
Signed-off-by: srinivas thaduvai <sthaduvai@nvidia.com>
Signed-off-by: Martin Chi <mchi@nvidia.com>
Reviewed-on: http://git-master/r/365808
| -rw-r--r-- | arch/arm/mach-tegra/tegra11x_usb_phy.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/tegra11x_usb_phy.c b/arch/arm/mach-tegra/tegra11x_usb_phy.c index e493a48dc8ca..bce29d06031a 100644 --- a/arch/arm/mach-tegra/tegra11x_usb_phy.c +++ b/arch/arm/mach-tegra/tegra11x_usb_phy.c @@ -245,6 +245,9 @@ #define UHSIC_RPU_DATA (1 << 11) #define UHSIC_RPU_STROBE (1 << 12) +#define UHSIC_SPARE_CFG0 0xc2c +#define FORCE_BK_ON (1 << 12) + #define UHSIC_STAT_CFG0 0xc28 #define UHSIC_CONNECT_DETECT (1 << 0) @@ -1825,6 +1828,11 @@ static int uhsic_phy_power_on(struct tegra_usb_phy *phy) val |= UHSIC_PD_TRK; writel(val, base + UHSIC_PADS_CFG1); + /* Enable bus keepers always */ + val = readl(base + UHSIC_SPARE_CFG0); + val |= FORCE_BK_ON; + writel(val, base + UHSIC_SPARE_CFG0); + /*SUSP_CTRL has to be toggled to enable host PHY clock */ val = readl(base + USB_SUSP_CTRL); val |= USB_SUSP_CLR; @@ -1929,7 +1937,7 @@ static int uhsic_phy_power_off(struct tegra_usb_phy *phy) val |= HOSTPC1_DEVLC_PHCD; writel(val, base + HOSTPC1_DEVLC); - /* Remove power downs for HSIC from PADS CFG1 register */ + /* Enable power downs for HSIC from PADS CFG1 register */ val = readl(base + UHSIC_PADS_CFG1); val |= (UHSIC_PD_BG | UHSIC_PD_TRK | UHSIC_PD_ZI | UHSIC_PD_TX); |