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authorAnshul Jain <anshulj@nvidia.com>2013-07-18 17:11:36 -0700
committerRiham Haidar <rhaidar@nvidia.com>2013-09-12 15:22:03 -0700
commit1583d3b4fbbdcf82efb61ba327d3a017fe7d3185 (patch)
treebc55654d0364849301516fc572093a769f5ca266
parent7c5cc228c4893919d6d6958f28a75096c3ae33e5 (diff)
regulator:palmas: Sysfs node to change smps45 mode
This change creates a sysfs node /sys/bus/platform/devices/palmas-pmic/auto_smps45_ctrl echo 1 : force multi phase mode echo 0: auto phase selection Bug 1323712 Change-Id: Ibbac78cf841b1cda3444ad388426a0da4a67c38a Signed-off-by: Anshul Jain <anshulj@nvidia.com> (cherry picked from commit 4bd6aa227ef632c0bf32761262799490c6aa33bf) Reviewed-on: http://git-master/r/253685 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
-rw-r--r--drivers/regulator/palmas-regulator.c60
1 files changed, 60 insertions, 0 deletions
diff --git a/drivers/regulator/palmas-regulator.c b/drivers/regulator/palmas-regulator.c
index ef061eb83f06..87c62aa68e7a 100644
--- a/drivers/regulator/palmas-regulator.c
+++ b/drivers/regulator/palmas-regulator.c
@@ -2,6 +2,7 @@
* Driver for Regulator part of Palmas PMIC Chips
*
* Copyright 2011-2012 Texas Instruments Inc.
+ * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
*
* Author: Graeme Gregory <gg@slimlogic.co.uk>
*
@@ -1272,6 +1273,59 @@ err:
return;
}
+
+static ssize_t auto_smps45_ctrl_set(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t count)
+{
+ unsigned int reg_val, ret_val;
+ long set_val;
+ struct palmas *palmas = dev_get_drvdata(dev->parent);
+ ret_val = palmas_smps_read(palmas, PALMAS_SMPS_CTRL, &reg_val);
+
+ if (ret_val < 0) {
+ dev_err(dev, "Not able to read registers\n");
+ goto out;
+ }
+
+ if (kstrtol(buf, 10, &set_val)) {
+ ret_val = -EINVAL;
+ goto out;
+ }
+
+ set_val = set_val > 0 ? 0x2 : 0;
+ reg_val = reg_val & (~PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK);
+ if (set_val) {
+ reg_val = reg_val |
+ (set_val << PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT);
+ }
+ ret_val = palmas_smps_write(palmas, PALMAS_SMPS_CTRL, reg_val);
+ if (ret_val < 0) {
+ dev_err(dev, "Not able to write palmas register\n");
+ goto out;
+ }
+ ret_val = count;
+out:
+ return ret_val;
+}
+
+static ssize_t auto_smps45_ctrl_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ unsigned int reg_val, ret_val;
+ struct palmas *palmas = dev_get_drvdata(dev->parent);
+ ret_val = palmas_smps_read(palmas, PALMAS_SMPS_CTRL, &reg_val);
+ if (ret_val < 0) {
+ dev_err(dev, "Not able to read palmas register");
+ return -EINVAL;
+ }
+ reg_val = (reg_val & PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK)
+ >> PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT;
+ return sprintf(buf, "%d\n", reg_val);
+}
+
+DEVICE_ATTR(auto_smps45_ctrl, 0644, auto_smps45_ctrl_show, \
+ auto_smps45_ctrl_set);
+
static __devinit int palmas_probe(struct platform_device *pdev)
{
struct palmas *palmas = dev_get_drvdata(pdev->dev.parent);
@@ -1482,6 +1536,12 @@ static __devinit int palmas_probe(struct platform_device *pdev)
}
}
+ if (device_create_file(&pdev->dev, &dev_attr_auto_smps45_ctrl)) {
+ dev_err(&pdev->dev, "failed to create sysfs\n");
+ ret = -ENOMEM;
+ goto err_unregister_regulator;
+ }
+
/* Check if LDO8 is in tracking mode or not */
if (pdata->enable_ldo8_tracking)
palmas_enable_ldo8_track(palmas);