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authorChristian Hemp <c.hemp@phytec.de>2013-07-17 21:51:04 +0200
committerJustin Waters <justin.waters@timesys.com>2013-11-07 12:19:34 -0500
commitf13c38714f8a4e638eebe9a483754a6d120a0eec (patch)
treeed584e33c094bfff608222759617caedf81d5dbd
parente26a512190c1f08b762968eabaa883c9435b7f91 (diff)
imx6q: Add module revison detection
The pin SD4_DAT4 until SD4_DAT7 be used as revison control. The pins will be internel pulled up so we read a 1111 for revison 1. For revison two the first pin (bit) is pulled down (see schematic pfla-02 page 4 "SDIO, NAND-Flash". On Module rev 1 the pins are connectet to the NAND but we have only 8bit NAND also the i.MX6 only can handle 8bit NAND flashs. Revisions: Rev 1: 0xF Rev 2: 0xE . . . Rev 15: 0x1 Rev 16: 0x0 Signed-off-by: Christian Hemp <c.hemp@phytec.de>
-rw-r--r--arch/arm/mach-mx6/board-mx6q_phyflex.h6
-rw-r--r--arch/arm/mach-mx6/board-mx6q_phytec-common.c21
-rw-r--r--arch/arm/mach-mx6/board-mx6q_phytec-common.h3
3 files changed, 30 insertions, 0 deletions
diff --git a/arch/arm/mach-mx6/board-mx6q_phyflex.h b/arch/arm/mach-mx6/board-mx6q_phyflex.h
index b4cc0b76bc3b..4605f80247f2 100644
--- a/arch/arm/mach-mx6/board-mx6q_phyflex.h
+++ b/arch/arm/mach-mx6/board-mx6q_phyflex.h
@@ -34,6 +34,12 @@
/* Common pads for PhyFlex board */
static iomux_v3_cfg_t mx6q_phytec_common_pads[] = {
+ /* GPIOs for revision control */
+ MX6Q_PAD_SD4_DAT4__GPIO_2_12,
+ MX6Q_PAD_SD4_DAT5__GPIO_2_13,
+ MX6Q_PAD_SD4_DAT6__GPIO_2_14,
+ MX6Q_PAD_SD4_DAT7__GPIO_2_15,
+
/* User LEDs */
MX6Q_PAD_ENET_TXD0__GPIO_1_30, // Led Green
MX6Q_PAD_EIM_EB3__GPIO_2_31, // Led Red
diff --git a/arch/arm/mach-mx6/board-mx6q_phytec-common.c b/arch/arm/mach-mx6/board-mx6q_phytec-common.c
index 85088b8fd348..b049f352301f 100644
--- a/arch/arm/mach-mx6/board-mx6q_phytec-common.c
+++ b/arch/arm/mach-mx6/board-mx6q_phytec-common.c
@@ -17,8 +17,10 @@
*/
#include <linux/clk.h>
+#include <linux/module.h>
#include <mach/common.h>
+#include <mach/gpio.h>
#include <mach/hardware.h>
#include <mach/iomux-mx6q.h>
@@ -29,9 +31,28 @@
/* Setup imx6 revision and uniq ID */
#define HW_OCOTP_DEVIDn(n) (0x00000410 + (n) * 0x10)
+
+unsigned int module_rev;
+EXPORT_SYMBOL(module_rev);
+
+static void get_module_revison(void)
+{
+ unsigned int val = 0;
+
+ val = gpio_get_value(IMX_GPIO_NR(2, 12));
+ val |= (gpio_get_value(IMX_GPIO_NR(2, 13)) << 1);
+ val |= (gpio_get_value(IMX_GPIO_NR(2, 14)) << 2);
+ val |= (gpio_get_value(IMX_GPIO_NR(2, 15)) << 3);
+
+ module_rev = 16 - val;
+
+}
+
void __init mx6_setup_cpuinfo(void)
{
system_rev = mx6q_revision();
system_serial_high = readl(MX6_IO_ADDRESS(OCOTP_BASE_ADDR) + HW_OCOTP_DEVIDn(0));
system_serial_low = readl(MX6_IO_ADDRESS(OCOTP_BASE_ADDR) + HW_OCOTP_DEVIDn(1));
+
+ get_module_revison();
}
diff --git a/arch/arm/mach-mx6/board-mx6q_phytec-common.h b/arch/arm/mach-mx6/board-mx6q_phytec-common.h
index b91ec4086dbd..6a21a17da195 100644
--- a/arch/arm/mach-mx6/board-mx6q_phytec-common.h
+++ b/arch/arm/mach-mx6/board-mx6q_phytec-common.h
@@ -3,6 +3,9 @@
#include <mach/iomux-mx6q.h>
+#define PHYFLEX_MODULE_REV_1 0x1
+#define PHYFLEX_MODULE_REV_2 0x2
+
extern __init void mx6_setup_cpuinfo(void);
#endif /* __BOARD_MX6Q_PHYTEC_COMMON_H__ */