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authorBhuvanchandra DV <bhuvanchandra.dv@toradex.com>2016-04-25 15:15:42 +0530
committerMarcel Ziswiler <marcel.ziswiler@toradex.com>2016-06-27 08:53:17 +0200
commitd2c90d0c0c9250444c52b6a828cc272bf0196857 (patch)
tree49efe3987f90e28a9b0370a024790a0caf95c40d
parent430c728373dac245d0ca55aac1d0fcc456872174 (diff)
imx: clk-vf610: Add clock for L2 switch
Add support for clock gating of the ESW(Ethernet switch) peripheral. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
-rw-r--r--drivers/clk/imx/clk-vf610.c1
-rw-r--r--include/dt-bindings/clock/vf610-clock.h3
2 files changed, 3 insertions, 1 deletions
diff --git a/drivers/clk/imx/clk-vf610.c b/drivers/clk/imx/clk-vf610.c
index f3b891999f41..8323efc46997 100644
--- a/drivers/clk/imx/clk-vf610.c
+++ b/drivers/clk/imx/clk-vf610.c
@@ -332,6 +332,7 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
clk[VF610_CLK_ENET_TS] = imx_clk_gate("enet_ts", "enet_ts_sel", CCM_CSCDR1, 23);
clk[VF610_CLK_ENET0] = imx_clk_gate2("enet0", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(0));
clk[VF610_CLK_ENET1] = imx_clk_gate2("enet1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(1));
+ clk[VF610_CLK_ESW] = imx_clk_gate2("esw", "ipg_bus", CCM_CCGR10, CCM_CCGRx_CGn(8));
clk[VF610_CLK_PIT] = imx_clk_gate2("pit", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(7));
diff --git a/include/dt-bindings/clock/vf610-clock.h b/include/dt-bindings/clock/vf610-clock.h
index da8c5c4ff46c..43c9e2282dae 100644
--- a/include/dt-bindings/clock/vf610-clock.h
+++ b/include/dt-bindings/clock/vf610-clock.h
@@ -199,6 +199,7 @@
#define VF610_CLK_TCON1 186
#define VF610_CLK_DDRMC 187
#define VF610_CLK_WKPU 188
-#define VF610_CLK_END 189
+#define VF610_CLK_ESW 189
+#define VF610_CLK_END 190
#endif /* __DT_BINDINGS_CLOCK_VF610_H */