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| author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2013-09-16 07:30:37 +0200 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2013-09-16 07:30:37 +0200 |
| commit | 06922aae13fd1c660712d85c7c237e00b10c4ddd (patch) | |
| tree | 563db8eab53dcd35d58d42b58b8286b68e749cc5 | |
| parent | d9902882cbc782df77cc43c2b370d7e94180bf73 (diff) | |
colibri_vf50: DCU: 30 MHz VESA VGA pixel clock
For now use a divider of 5 in order to get a pixel clock of 30 MHz
required for VESA VGA.
| -rw-r--r-- | drivers/video/mvf_dcu.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/video/mvf_dcu.c b/drivers/video/mvf_dcu.c index 44d93d6534e0..ac30b50364a4 100644 --- a/drivers/video/mvf_dcu.c +++ b/drivers/video/mvf_dcu.c @@ -454,7 +454,11 @@ static void update_lcdc(struct fb_info *info) writel(DCU_MODE_BLEND_ITER(3) | DCU_MODE_RASTER_EN(1), dcu->base + DCU_DCU_MODE); +#if defined(CONFIG_MACH_COLIBRI_VF50) + writel(5, dcu->base + DCU_DIV_RATIO); +#else writel(9, dcu->base + DCU_DIV_RATIO); +#endif writel(DCU_SYN_POL_INV_PXCK(0) | DCU_SYN_POL_NEG(0) | DCU_SYN_POL_INV_VS(1) | DCU_SYN_POL_INV_HS(1), |