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authorStefan Agner <stefan.agner@toradex.com>2017-03-03 19:23:05 -0800
committerMarcel Ziswiler <marcel.ziswiler@toradex.com>2017-04-03 15:13:06 +0200
commit3e92301d12417baf5ed424da3a64081243eda2c2 (patch)
tree12559c08a7183d26efd296a21bc6ff04ea5364fa
parent0666dae4b839135b6441b773b7ec9a24b0fb93ad (diff)
ARM: imx: busfreq: request bus frequency depending on M4 clock
Only request high bus frequency for Cortex-M4 if the Cortex-M4 is running in a high frequency mode. The Cortex-M4 clock is not directly connected with the bus frequency, however, we assume that when the M4 CPU is running at lower frequency a lower bus speed is sufficient too. The driver already has been doing this on i.MX 6SoloX, this change applies the same logic to i.MX 7. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
-rw-r--r--arch/arm/mach-imx/busfreq-imx.c8
1 files changed, 3 insertions, 5 deletions
diff --git a/arch/arm/mach-imx/busfreq-imx.c b/arch/arm/mach-imx/busfreq-imx.c
index 8bafe4bf05a3..f1326582ca44 100644
--- a/arch/arm/mach-imx/busfreq-imx.c
+++ b/arch/arm/mach-imx/busfreq-imx.c
@@ -1085,7 +1085,7 @@ static int busfreq_probe(struct platform_device *pdev)
}
}
- if (cpu_is_imx6sx()) {
+ if (cpu_is_imx6sx() || cpu_is_imx7d()) {
m4_clk = devm_clk_get(&pdev->dev, "m4");
if (IS_ERR(m4_clk)) {
dev_err(busfreq_dev, "%s: failed to get m4 clk.\n", __func__);
@@ -1225,17 +1225,15 @@ static int busfreq_probe(struct platform_device *pdev)
err = init_mmdc_lpddr2_settings(pdev);
}
- if (cpu_is_imx6sx()) {
+ if (cpu_is_imx6sx() || cpu_is_imx7d()) {
/* if M4 is enabled and rate > 24MHz, add high bus count */
if (imx_src_is_m4_enabled() &&
(clk_get_rate(m4_clk) > LPAPM_CLK))
high_bus_count++;
}
- if (cpu_is_imx7d() && imx_src_is_m4_enabled()) {
- high_bus_count++;
+ if (cpu_is_imx7d() && imx_src_is_m4_enabled())
imx_mu_lpm_ready(true);
- }
if (err) {
dev_err(busfreq_dev, "Busfreq init of ddr controller failed\n");