diff options
| author | Max Krummenacher <max.krummenacher@toradex.com> | 2016-09-17 00:34:03 +0200 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2017-01-10 23:13:29 +0100 |
| commit | 257fabb206a34cc070a4d6b14c0c732808ad836c (patch) | |
| tree | e262401db95a6070e591d87a3e4a2e1b9f53f3a8 | |
| parent | d1c393ddcb6937b58fa3a9314c8b6f2382b346dc (diff) | |
tty: serial: imx: disable DCD and RI interrupts
Move the solution from a83490c48b69b7a913f1cb7595a052d3a9166c5c to a
location executed before the UART interrupt gets requested.
Withour this, on a i.MX6 DL, the kernel did block before any console
output appeared.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
| -rw-r--r-- | drivers/tty/serial/imx.c | 19 |
1 files changed, 12 insertions, 7 deletions
diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c index 2b87876d0bd9..63110b122947 100644 --- a/drivers/tty/serial/imx.c +++ b/drivers/tty/serial/imx.c @@ -1134,13 +1134,6 @@ static int imx_startup(struct uart_port *port) writel(temp & ~UCR4_DREN, sport->port.membase + UCR4); - /* Disable DCDDELT/RIDELT interrupts */ - if (!is_imx1_uart(sport) && sport->dte_mode) { - temp = readl(sport->port.membase + UCR3); - temp &= ~(UCR3_DCD | UCR3_RI); - writel(temp, sport->port.membase + UCR3); - } - /* Reset fifo's and state machines */ i = 100; @@ -2039,6 +2032,18 @@ static int serial_imx_probe(struct platform_device *pdev) } sport->port.uartclk = clk_get_rate(sport->clk_per); + /* if DTE mode is requested, make sure DTE mode is selected + and then disable DCDDELT/RIDELT interrupts */ + if (!is_imx1_uart(sport) && sport->dte_mode) { + unsigned long temp; + temp = readl(sport->port.membase + UFCR); + temp |= UFCR_DCEDTE; + writel(temp, sport->port.membase + UFCR); + temp = readl(sport->port.membase + UCR3); + temp &= ~(UCR3_DCD | UCR3_RI); + writel(temp, sport->port.membase + UCR3); + } + /* * Allocate the IRQ(s) i.MX1 has three interrupts whereas later * chips only have one interrupt. |