diff options
| author | Liu Ying <Ying.Liu@freescale.com> | 2013-03-08 16:44:41 +0800 |
|---|---|---|
| committer | Liu Ying <Ying.Liu@freescale.com> | 2014-03-17 11:41:10 +0800 |
| commit | 3e67a6ae4473736e3d6d3784f03a1dc78c37e739 (patch) | |
| tree | 9c3722e918fb4ed6564878c485027d2785069180 | |
| parent | 74135f03031d74eff516d61f20c3cf86894d99da (diff) | |
ENGR00243315-3 MXC V4L2 Capture:Remove unnecessary mclk setting
commit f8e1a3bb62eecf93a31a51c4dbe08a0214fa1d57 added a hard
coding for csi_parma.mclk setting to 27MHz. The comment added by
that commit is totally wrong by telling that csi_param.mclk
would be a kind of 'pixel clock' set in 'csi_data_dest' register.
This patch removes the unnecessary mclk setting for csi_param.mclk
variable, since it is only valid for CSI test mode.
Conflicts:
drivers/media/video/mxc/capture/mxc_v4l2_capture.c
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit bb5afd554c50b639f1e1b94481b24f35ae8c4dc5)
| -rwxr-xr-x | drivers/media/platform/mxc/capture/mxc_v4l2_capture.c | 14 |
1 files changed, 3 insertions, 11 deletions
diff --git a/drivers/media/platform/mxc/capture/mxc_v4l2_capture.c b/drivers/media/platform/mxc/capture/mxc_v4l2_capture.c index db64674e45c7..e4eea5309e57 100755 --- a/drivers/media/platform/mxc/capture/mxc_v4l2_capture.c +++ b/drivers/media/platform/mxc/capture/mxc_v4l2_capture.c @@ -1,5 +1,5 @@ /* - * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -1354,19 +1354,11 @@ static int mxc_v4l2_s_param(cam_data *cam, struct v4l2_streamparm *parm) csi_param.csi = cam->csi; csi_param.mclk = 0; - /*This may not work on other platforms. Check when adding a new one.*/ - /*The mclk clock was never set correclty in the ipu register*/ - /*for now we are going to use this mclk as pixel clock*/ - /*to set csi0_data_dest register.*/ - /*This is a workaround which should be fixed*/ pr_debug(" clock_curr=mclk=%d\n", ifparm.u.bt656.clock_curr); - if (ifparm.u.bt656.clock_curr == 0) { + if (ifparm.u.bt656.clock_curr == 0) csi_param.clk_mode = IPU_CSI_CLK_MODE_CCIR656_INTERLACED; - /*protocol bt656 use 27Mhz pixel clock */ - csi_param.mclk = 27000000; - } else { + else csi_param.clk_mode = IPU_CSI_CLK_MODE_GATED_CLK; - } csi_param.pixclk_pol = ifparm.u.bt656.latch_clk_inv; |