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authorRanjani Vaidyanathan <ra5478@freescale.com>2011-03-22 11:30:53 -0500
committerAndy Voltz <andy.voltz@timesys.com>2011-06-01 13:21:07 -0400
commit0775c6e5e57e6e87cd8a1b557e2fe07b7a7477fd (patch)
treecc2cdb3035f961a9bcb69c99d7594df3de0a7de7
parent27a4c531a3b9822fc5cd4d627d994e90e63c43e0 (diff)
ENGR00140875: MX51: Added 400MHz working point
Added 400MHz to the cpu_wp_tbl and to the dvfs_core_setpoint arrays. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
-rw-r--r--arch/arm/mach-mx5/mx51_babbage.c24
1 files changed, 19 insertions, 5 deletions
diff --git a/arch/arm/mach-mx5/mx51_babbage.c b/arch/arm/mach-mx5/mx51_babbage.c
index bfae2d960223..90528c246576 100644
--- a/arch/arm/mach-mx5/mx51_babbage.c
+++ b/arch/arm/mach-mx5/mx51_babbage.c
@@ -240,12 +240,13 @@ static iomux_v3_cfg_t mx51babbage_pads[] = {
};
static struct dvfs_wp dvfs_core_setpoint[] = {
- {33, 8, 33, 10, 10, 0x08},
- {26, 0, 33, 20, 10, 0x08},
- {28, 8, 33, 20, 30, 0x08},
- {29, 0, 33, 20, 10, 0x08},};
+ {33, 13, 33, 10, 10, 0x08}, /* 800MHz*/
+ {28, 8, 33, 10, 10, 0x08}, /* 400MHz */
+ {20, 0, 33, 20, 10, 0x08}, /* 160MHz*/
+ {28, 8, 33, 20, 30, 0x08}, /*160MHz, AHB 133MHz, LPAPM mode*/
+ {29, 0, 33, 20, 10, 0x08},}; /* 160MHz, AHB 24MHz */
-/* working point(wp): 0 - 800MHz; 1 - 166.25MHz; */
+/* CPU working point(wp) */
static struct cpu_wp cpu_wp_auto[] = {
{
.pll_rate = 1000000000,
@@ -267,7 +268,20 @@ static struct cpu_wp cpu_wp_auto[] = {
.cpu_voltage = 1100000,},
{
.pll_rate = 800000000,
+ .cpu_rate = 400000000,
+ .pdf = 0,
+ .mfi = 8,
+ .mfd = 2,
+ .mfn = 1,
+ .cpu_podf = 1,
+ .cpu_voltage = 950000,},
+ {
+ .pll_rate = 800000000,
.cpu_rate = 166250000,
+ .pdf = 0,
+ .mfi = 8,
+ .mfd = 2,
+ .mfn = 1,
.cpu_podf = 4,
.cpu_voltage = 850000,},
};