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authorNiu <b23300@freescale.com>2009-08-06 23:13:23 +0800
committerJustin Waters <justin.waters@timesys.com>2009-10-13 11:05:01 -0400
commitef2ef8e9fba5a163b526e1e0b05dcc87ea6bb878 (patch)
tree6ff0c777d53549cc80e67e81446796d1f5e2cbf1
parentc7573c68f075f66c7ec584fb69ec900c35544949 (diff)
ENGR00114905 MX25: Fix touch screen failure case
LCDC clock must be derived from UPLL clock. Signed-off-by: Niu Xule <b23300@freescale.com>
-rw-r--r--arch/arm/mach-mx25/clock.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c
index 03a2a6af9796..163c3bba219c 100644
--- a/arch/arm/mach-mx25/clock.c
+++ b/arch/arm/mach-mx25/clock.c
@@ -548,7 +548,7 @@ static struct clk per_clk[] = {
{
.name = "per_lcdc_clk",
.id = 7,
- .parent = &ahb_clk, /* can be AHB or UPLL */
+ .parent = &upll_clk, /* Must be UPLL */
.round_rate = _clk_perclkx_round_rate,
.set_rate = _clk_perclkx_set_rate,
.set_parent = _clk_perclkx_set_parent,
@@ -1702,6 +1702,10 @@ int __init mxc_clocks_init(unsigned long ckil, unsigned long osc, unsigned long
/* GPT clock must be derived from AHB clock */
clk_set_rate(&per_clk[5], ahb_clk.rate / 10);
+ /* LCDC clock must be derived from UPLL clock */
+ clk_set_parent(&per_clk[7], &upll_clk);
+ clk_set_rate(&per_clk[7], upll_clk.rate);
+
/* the NFC clock must be derived from AHB clock */
clk_set_parent(&per_clk[8], &ahb_clk);
clk_set_rate(&per_clk[8], ahb_clk.rate / 6);