diff options
| author | Ranjani Vaidyanathan-RA5478 <Ranjani.Vaidyanathan@freescale.com> | 2009-08-13 21:27:27 -0500 |
|---|---|---|
| committer | Justin Waters <justin.waters@timesys.com> | 2009-10-13 11:05:12 -0400 |
| commit | b255fbbef7c2dddfdce9c3805e1dcb782381faa3 (patch) | |
| tree | 5af39be640c62094db956dee5077d8322845a8bf | |
| parent | 174c55af186bdbe2829ba5bd65e348a4bedb61f7 (diff) | |
ENGR00115334: MX51: Donot scale arm_axi_clk in peripheral bus scaling.
Scaline arm_axi clock can impact GP power number, so leave it at 166.25MHz.
Also donot lower peripheral bus frequency when ARM is at high frequency
setpoint.
Signed-off-by: Ranjani Vaidyanathan-RA5478 <Ranjani.Vaidyanathan@freescale.com>
(cherry picked from commit 19a023e83be38efa1f393fa31ecdec3506a9f2d3)
| -rw-r--r-- | arch/arm/mach-mx51/bus_freq.c | 26 |
1 files changed, 16 insertions, 10 deletions
diff --git a/arch/arm/mach-mx51/bus_freq.c b/arch/arm/mach-mx51/bus_freq.c index bb46dd7af7c1..da31595832dc 100644 --- a/arch/arm/mach-mx51/bus_freq.c +++ b/arch/arm/mach-mx51/bus_freq.c @@ -49,7 +49,7 @@ struct clk *pll2; struct clk *main_bus_clk; struct clk *axi_a_clk; struct clk *axi_b_clk; -struct clk *pll1_sw_clk; +struct clk *cpu_clk; struct clk *ddr_hf_clk; struct clk *nfc_clk; struct clk *ahb_clk; @@ -68,10 +68,13 @@ int bus_freq_scaling_is_active; char *gp_reg_id = "SW1"; char *lp_reg_id = "SW2"; +static struct cpu_wp *cpu_wp_tbl; static struct device *busfreq_dev; extern int lp_high_freq; extern int lp_med_freq; extern int dvfs_core_is_active; +extern struct cpu_wp *(*get_cpu_wp)(int *wp); +extern int cpu_wp_nr; struct dvfs_wp dvfs_core_setpoint[] = {{33, 7, 33, 20, 20, 0x10}, {27, 0, 33, 20, 20, 0x10},}; @@ -137,12 +140,17 @@ int set_high_bus_freq(int high_bus_freq) low_bus_freq_mode = 0; } + /* + * If the CPU freq is 800MHz, set the bus to the high setpoint + * (133MHz) and DDR to 200MHz. + */ + if (clk_get_rate(cpu_clk) != cpu_wp_tbl[cpu_wp_nr - 1].cpu_rate) + high_bus_freq = 1; + if (((clk_get_rate(ahb_clk) == LP_MED_CLK) && lp_high_freq) || high_bus_freq) { /* Set to the high setpoint. */ high_bus_freq_mode = 1; - clk_set_rate(axi_a_clk, - clk_round_rate(axi_a_clk, AXI_A_NORMAL_CLK)); clk_set_rate(ahb_clk, clk_round_rate(ahb_clk, LP_NORMAL_CLK)); clk_set_rate(ddr_hf_clk, @@ -155,8 +163,6 @@ int set_high_bus_freq(int high_bus_freq) low_bus_freq_mode = 0; clk_set_rate(ddr_hf_clk, clk_round_rate(ddr_hf_clk, DDR_LOW_FREQ_CLK)); - clk_set_rate(axi_a_clk, - clk_round_rate(axi_a_clk, LP_MED_CLK)); clk_set_rate(ahb_clk, clk_round_rate(ahb_clk, LP_MED_CLK)); } @@ -291,11 +297,11 @@ static int __devinit busfreq_probe(struct platform_device *pdev) return PTR_ERR(ddr_clk); } - pll1_sw_clk = clk_get(NULL, "pll1_sw_clk"); - if (IS_ERR(pll1_sw_clk)) { - printk(KERN_DEBUG "%s: failed to get pll1_sw_clk\n", + cpu_clk = clk_get(NULL, "cpu_clk"); + if (IS_ERR(cpu_clk)) { + printk(KERN_DEBUG "%s: failed to get cpu_clk\n", __func__); - return PTR_ERR(pll1_sw_clk); + return PTR_ERR(cpu_clk); } ipu_clk = clk_get(NULL, "ipu_clk"); @@ -338,7 +344,7 @@ static int __devinit busfreq_probe(struct platform_device *pdev) "Unable to register sysdev entry for BUSFREQ"); return err; } - + cpu_wp_tbl = get_cpu_wp(&cpu_wp_nr); low_bus_freq_mode = 0; high_bus_freq_mode = 0; bus_freq_scaling_is_active = 0; |