ENGR00114937: MX51: Move USBOH3 and USB-PHY to source from PLL2 and 24MHz.

Moved usboh3 clock to source from pll2.
Moved internal usb-phy clock to source from 24MHz oscillator.
Also fixed bugs associated with SW frequency scaling on peripheral domain.

Signed-off-by: Ranjani Vaidyanathan-RA5478 <Ranjani.Vaidyanathan@freescale.com>

3 files changed, 25 insertions, 17 deletions

diff --git a/arch/arm/mach-mx51/bus_freq.c b/arch/arm/mach-mx51/bus_freq.c
index 77cf5f57c9b9..bcdbbc6dfdde 100644
--- a/arch/arm/mach-mx51/bus_freq.c
+++ b/arch/arm/mach-mx51/bus_freq.c
@@ -144,12 +144,12 @@ int set_high_bus_freq(int high_bus_freq)
 			clk_set_rate(axi_a_clk,
 				   clk_round_rate(axi_a_clk, AXI_A_NORMAL_CLK));
 			clk_set_rate(ahb_clk,
-				clk_round_rate(axi_b_clk, LP_NORMAL_CLK));
+				clk_round_rate(ahb_clk, LP_NORMAL_CLK));
 			clk_set_rate(ddr_hf_clk,
 				clk_round_rate(ddr_hf_clk, DDR_NORMAL_CLK));
 
 		}
-		if (lp_med_freq && !lp_high_freq && !high_bus_freq) {
+		if (!lp_high_freq && !high_bus_freq) {
 			/* Set to the medium setpoint. */
 			high_bus_freq_mode = 0;
 			low_bus_freq_mode = 0;
@@ -158,7 +158,7 @@ int set_high_bus_freq(int high_bus_freq)
 			clk_set_rate(axi_a_clk,
 				     clk_round_rate(axi_a_clk, LP_MED_CLK));
 			clk_set_rate(ahb_clk,
-				     clk_round_rate(axi_b_clk, LP_MED_CLK));
+				     clk_round_rate(ahb_clk, LP_MED_CLK));
 		}
 	}
 
diff --git a/arch/arm/mach-mx51/clock.c b/arch/arm/mach-mx51/clock.c
index 8426d7a968eb..cbe2b02b341e 100644
--- a/arch/arm/mach-mx51/clock.c
+++ b/arch/arm/mach-mx51/clock.c
@@ -2450,22 +2450,21 @@ static struct clk usboh3_clk[] = {
 	 .enable_shift = MXC_CCM_CCGR2_CG14_OFFSET,
 	 .disable = _clk_disable,
 	 .secondary = &usboh3_clk[1],
-	 .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
+	 .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE,
 	 },
 	{
+	 .name = "usb_sec_clk",
+	 .parent = &tmax2_clk,
+	 .secondary = &emi_fast_clk,
+	 },
+};
+static struct clk usb_ahb_clk = {
 	 .name = "usb_ahb_clk",
 	 .parent = &ipg_clk,
 	 .enable = _clk_enable,
 	 .enable_reg = MXC_CCM_CCGR2,
 	 .enable_shift = MXC_CCM_CCGR2_CG13_OFFSET,
 	 .disable = _clk_disable,
-	 .secondary = &usboh3_clk[2],
-	 },
-	{
-	 .name = "usb_sec_clk",
-	 .parent = &tmax2_clk,
-	 .secondary = &emi_fast_clk,
-	 },
 };
 
 static void _clk_usb_phy_recalc(struct clk *clk)
@@ -3400,7 +3399,7 @@ static struct clk *mxc_clks[] = {
 	&tmax3_clk,
 	&usboh3_clk[0],
 	&usboh3_clk[1],
-	&usboh3_clk[2],
+	&usb_ahb_clk,
 	&usb_phy_clk,
 	&usb_utmi_clk,
 	&usb_clk,
@@ -3654,6 +3653,18 @@ int __init mxc_clocks_init(unsigned long ckil, unsigned long osc, unsigned long
 	clk_set_parent(&ssi_ext1_clk, &ssi1_clk[0]);
 	clk_set_parent(&ssi_ext2_clk, &ssi2_clk[0]);
 
+	/* move usb_phy_clk to 24MHz */
+	clk_set_parent(&usb_phy_clk, &osc_clk);
+
+	/* set usboh3_clk to pll2 */
+	clk_set_parent(&usboh3_clk, &pll2_sw_clk);
+	reg = __raw_readl(MXC_CCM_CSCDR1);
+	reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK;
+	reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK;
+	reg |= 4 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET;
+	reg |= 1 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET;
+	__raw_writel(reg, MXC_CCM_CSCDR1);
+
 	/* Set the current working point. */
 	cpu_wp_tbl = get_cpu_wp(&cpu_wp_nr);
 	/* Update the cpu working point table based on the PLL1 freq
diff --git a/arch/arm/plat-mxc/cpufreq.c b/arch/arm/plat-mxc/cpufreq.c
index 740aace213b0..bc489dff686a 100644
--- a/arch/arm/plat-mxc/cpufreq.c
+++ b/arch/arm/plat-mxc/cpufreq.c
@@ -189,7 +189,6 @@ static int mxc_set_target(struct cpufreq_policy *policy,
 	freqs.cpu = 0;
 	freqs.flags = 0;
 	low_freq_bus_ready = low_freq_bus_used();
-
 	cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
 	if (!dvfs_core_is_active) {
 		if ((freq_Hz == arm_lpm_clk) && (!low_bus_freq_mode)
@@ -199,9 +198,7 @@ static int mxc_set_target(struct cpufreq_policy *policy,
 			set_low_bus_freq();
 
 		} else {
-			if (low_bus_freq_mode) {
-				set_high_bus_freq(0);
-			}
+			set_high_bus_freq(0);
 			ret = set_cpu_freq(freq_Hz);
 		}
 	}
@@ -313,7 +310,7 @@ static int mxc_cpufreq_driver_exit(struct cpufreq_policy *policy)
 	if (!dvfs_core_is_active)
 		set_cpu_freq(arm_normal_clk);
 	if (!high_bus_freq_mode)
-		set_high_bus_freq(0);
+		set_high_bus_freq(1);
 
 	clk_put(cpu_clk);
 	regulator_put(gp_regulator);