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authorXiexiaobo <X.Xie@freescale.com>2009-08-04 11:23:07 +0800
committerJustin Waters <justin.waters@timesys.com>2009-10-13 11:04:55 -0400
commit44bef6b6cef552dbede5443cb9d2732a804a5170 (patch)
treecb90f5bf196f318b3837260e55ef249e485e1d15
parent8014d65d3266ce048b8c9d7b34ac4a268f3626df (diff)
ENGR00113292 MX25: Set GPT clock's parent to ahb_clk
Set GPT clock's parent to ahb_clk for i.MX25. Signed-off-by: Niu Xule <b23300@freescale.com>
-rw-r--r--arch/arm/mach-mx25/clock.c5
-rw-r--r--arch/arm/plat-mxc/include/mach/mx25.h2
2 files changed, 5 insertions, 2 deletions
diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c
index 4a1f9ddcf9cf..03a2a6af9796 100644
--- a/arch/arm/mach-mx25/clock.c
+++ b/arch/arm/mach-mx25/clock.c
@@ -526,7 +526,7 @@ static struct clk per_clk[] = {
{
.name = "per_gpt_clk",
.id = 5,
- .parent = &upll_clk, /* can be AHB or UPLL */
+ .parent = &ahb_clk, /* Must be AHB */
.round_rate = _clk_perclkx_round_rate,
.set_rate = _clk_perclkx_set_rate,
.set_parent = _clk_perclkx_set_parent,
@@ -1699,6 +1699,9 @@ int __init mxc_clocks_init(unsigned long ckil, unsigned long osc, unsigned long
propagate_rate(&osc24m_clk);
propagate_rate(&osc32k_clk);
+ /* GPT clock must be derived from AHB clock */
+ clk_set_rate(&per_clk[5], ahb_clk.rate / 10);
+
/* the NFC clock must be derived from AHB clock */
clk_set_parent(&per_clk[8], &ahb_clk);
clk_set_rate(&per_clk[8], ahb_clk.rate / 6);
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
index b77040783581..a1c841c647c4 100644
--- a/arch/arm/plat-mxc/include/mach/mx25.h
+++ b/arch/arm/plat-mxc/include/mach/mx25.h
@@ -28,7 +28,7 @@
/*!
* defines the OS clock tick rate
*/
-#define CLOCK_TICK_RATE 12000000
+#define CLOCK_TICK_RATE 13300000
/*!
* Register an interrupt handler for the SMN as well as the SCC. In some