diff options
| author | Wallace Wang <r59996@freescale.com> | 2009-08-05 17:55:59 +0000 |
|---|---|---|
| committer | Justin Waters <justin.waters@timesys.com> | 2009-10-13 11:05:00 -0400 |
| commit | 314cd97bff200a275be658590a1d48b096842c8d (patch) | |
| tree | 434f31a3c88d85b56acf8520773f3c1242bc9ecb | |
| parent | 4e539ddd1ed4dc18d7047e414feefb4ce7897963 (diff) | |
ENGR00114851 MX51: Fix SSI1 SDMA data transfer failure
The root cause is that CCGR5 [12 - 13] is defalut set as 00
to save power. ipmux clock will be enabled when MCU read/write
data from AIPS_TZ, while SDMA read/write data from AIPS_TZ can't
enable the ipmux clock when MCU in WAIT mode.
"Bit 12 affects ipmux1 via spare_output_1, and Bit 13 affects
ipmux2 via spare_output_2. The default value of those bits is 11
For the default case, CCM will generate 1 for both spare_output_1
and spare_output_2. If either one of those bits will be set to 0,
then the corresponding output will be set to 0 when system enters
WAIT mode. This will allow system to turn off the IPMUX clocks
in WAIT mode and can be used in LP-APM to preserve the IPMUX power
if no accesses are expected on the IP bus. In run mode the IPMUX
clocks will not be closed and the setting of those bits will not
affect RUN mode."
Signed-off-by: Wallace Wang <r59996@freescale.com>
| -rw-r--r-- | arch/arm/mach-mx51/clock.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-mx51/clock.c b/arch/arm/mach-mx51/clock.c index 566926f046c2..8426d7a968eb 100644 --- a/arch/arm/mach-mx51/clock.c +++ b/arch/arm/mach-mx51/clock.c @@ -3555,6 +3555,7 @@ int __init mxc_clocks_init(unsigned long ckil, unsigned long osc, unsigned long __raw_writel(1 << MXC_CCM_CCGR4_CG8_OFFSET, MXC_CCM_CCGR4); __raw_writel(1 << MXC_CCM_CCGR5_CG2_OFFSET | + 3 << MXC_CCM_CCGR5_CG6_OFFSET | 1 << MXC_CCM_CCGR5_CG7_OFFSET | 1 << MXC_CCM_CCGR5_CG8_OFFSET | 3 << MXC_CCM_CCGR5_CG9_OFFSET | |