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authorQuinn Jensen <quinn.jensen@freescale.com>2007-10-24 21:26:39 -0600
committerQuinn Jensen <quinn.jensen@freescale.com>2007-10-24 21:26:39 -0600
commitc8ebc96d995f386afea6e24766153c199b1a8ca8 (patch)
treeb2bb85ab5353c3d4545dcdbf744b30f550ae9de7
parent0c129f1be7a29163e62899254326d8d15a9d3ef9 (diff)
CR ENGR00052743 Reset CSPI On MX27
Patch for CR ENGR00052743: Reset the CSPI module for MX27 before initializing it. Applies to linux 2.6.22 kernel for MX platforms. http://www.bitshrine.org/gpp/linux-2.6.22-mx-CR-ENGR00052743-Reset-CSPI-On-MX27.patch
-rw-r--r--drivers/spi/mxc_spi.c3
-rw-r--r--drivers/spi/mxc_spi.h4
-rw-r--r--drivers/spi/mxc_spi_mx27.h8
3 files changed, 11 insertions, 4 deletions
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index 800d19fabfc3..54ffc54c10f1 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -668,6 +668,9 @@ static int mxc_spi_probe(struct platform_device *pdev)
clk_enable(master_drv_data->clk);
master_drv_data->spi_ipg_clk = clk_get_rate(master_drv_data->clk);
+ __raw_writel(MXC_CSPIRESET_START,
+ master_drv_data->base + MXC_CSPIRESET);
+ udelay(1);
__raw_writel(MXC_CSPICTRL_ENABLE | MXC_CSPICTRL_MASTER,
master_drv_data->base + MXC_CSPICTRL);
__raw_writel(MXC_CSPIPERIOD_32KHZ,
diff --git a/drivers/spi/mxc_spi.h b/drivers/spi/mxc_spi.h
index 6316282d6cff..42b177493f79 100644
--- a/drivers/spi/mxc_spi.h
+++ b/drivers/spi/mxc_spi.h
@@ -113,6 +113,8 @@
#define MXC_CSPITEST_LBC (1 << 14)
+#define MXC_CSPIRESET_START 1
+
/*!
* @struct mxc_spi_unique_def
* @brief This structure contains information that differs with
@@ -140,7 +142,7 @@ struct mxc_spi_unique_def {
*/
unsigned int drctrl_shift;
/*!
- * Transfer Complete shift.
+ * Transfer Complete shift.
*/
unsigned int xfer_complete;
/*!
diff --git a/drivers/spi/mxc_spi_mx27.h b/drivers/spi/mxc_spi_mx27.h
index 2323cd96e494..06921f3dacd9 100644
--- a/drivers/spi/mxc_spi_mx27.h
+++ b/drivers/spi/mxc_spi_mx27.h
@@ -50,8 +50,8 @@
#define MXC_CSPICTRL_MAXDATRATE 0x10
#define MXC_CSPICTRL_DATAMASK 0x1F
#define MXC_CSPICTRL_DATASHIFT 14
-/* This adjustment in the shift is valid only for even states only(i.e. divide
- ratio of 2). SDHC_SPIEN is not set by default. If SDHC_SPIEN bit is set in
+/* This adjustment in the shift is valid only for even states only(i.e. divide
+ ratio of 2). SDHC_SPIEN is not set by default. If SDHC_SPIEN bit is set in
MXC_CSPICTRL, then divide ratio is 3, this shift adjustment is invalid. */
#define MXC_CSPICTRL_ADJUST_SHIFT(x) ((x) = ((x) - 1) * 2)
@@ -115,6 +115,8 @@
#define MXC_CSPITEST_LBC (1 << 14)
+#define MXC_CSPIRESET_START 1
+
/*!
* @struct mxc_spi_unique_def
* @brief This structure contains information that differs with
@@ -142,7 +144,7 @@ struct mxc_spi_unique_def {
*/
unsigned int drctrl_shift;
/*!
- * Transfer Complete shift.
+ * Transfer Complete shift.
*/
unsigned int xfer_complete;
/*!