update: gpio numober abc.. to 0123..

4 files changed, 76 insertions, 76 deletions

diff --git a/arch/arm/mach-mvf/devices.c b/arch/arm/mach-mvf/devices.c
index dcb41aba7110..0984259b10bc 100644
--- a/arch/arm/mach-mvf/devices.c
+++ b/arch/arm/mach-mvf/devices.c
@@ -36,42 +36,42 @@
 
 static struct mvf_gpio_port mvf_gpio_ports[] = {
 	{
-		.chip.label = "gpio-a",
-		.gbase = MVF_IO_ADDRESS(GPIOA_BASE_ADDR),
-		.pbase = MVF_IO_ADDRESS(MVF_PORT_A_BASE_ADDR),
+		.chip.label = "gpio-0",
+		.gbase = MVF_IO_ADDRESS(GPIO0_BASE_ADDR),
+		.pbase = MVF_IO_ADDRESS(MVF_PORT_0_BASE_ADDR),
 		.ibase = MVF_IO_ADDRESS(MVF_IOMUXC_BASE_ADDR),
 		.irq =MXC_INT_GPIOA,
 		.virtual_irq_start = MXC_GPIO_IRQ_START
 	},
 	{
-		.chip.label = "gpio-b",
-		.gbase = MVF_IO_ADDRESS(GPIOB_BASE_ADDR),
-		.pbase = MVF_IO_ADDRESS(MVF_PORT_B_BASE_ADDR),
+		.chip.label = "gpio-1",
+		.gbase = MVF_IO_ADDRESS(GPIO1_BASE_ADDR),
+		.pbase = MVF_IO_ADDRESS(MVF_PORT_1_BASE_ADDR),
 		.ibase = MVF_IO_ADDRESS(MVF_IOMUXC_BASE_ADDR),
 		.irq = MXC_INT_GPIOB,
 		.virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 1
 	},
 	{
-		.chip.label = "gpio-c",
-		.gbase = MVF_IO_ADDRESS(GPIOC_BASE_ADDR),
-		.pbase = MVF_IO_ADDRESS(MVF_PORT_C_BASE_ADDR),
+		.chip.label = "gpio-2",
+		.gbase = MVF_IO_ADDRESS(GPIO2_BASE_ADDR),
+		.pbase = MVF_IO_ADDRESS(MVF_PORT_2_BASE_ADDR),
 		.ibase = MVF_IO_ADDRESS(MVF_IOMUXC_BASE_ADDR),
 		.irq = MXC_INT_GPIOC,
 		.virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 2
 	},
 	{
-		.chip.label = "gpio-d",
-		.gbase = MVF_IO_ADDRESS(GPIOD_BASE_ADDR),
-		.pbase = MVF_IO_ADDRESS(MVF_PORT_D_BASE_ADDR),
+		.chip.label = "gpio-3",
+		.gbase = MVF_IO_ADDRESS(GPIO3_BASE_ADDR),
+		.pbase = MVF_IO_ADDRESS(MVF_PORT_3_BASE_ADDR),
 		.ibase = MVF_IO_ADDRESS(MVF_IOMUXC_BASE_ADDR),
 		.irq = MXC_INT_GPIOD,
 		//.irq_high = MXC_INT_GPIO4_INT31_16_NUM,
 		.virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 3
 	},
 	{
-		.chip.label = "gpio-e",
-		.gbase = MVF_IO_ADDRESS(GPIOE_BASE_ADDR),
-		.pbase = MVF_IO_ADDRESS(MVF_PORT_E_BASE_ADDR),
+		.chip.label = "gpio-4",
+		.gbase = MVF_IO_ADDRESS(GPIO4_BASE_ADDR),
+		.pbase = MVF_IO_ADDRESS(MVF_PORT_4_BASE_ADDR),
 		.ibase = MVF_IO_ADDRESS(MVF_IOMUXC_BASE_ADDR),
 		.irq = MXC_INT_GPIOE,
 		.virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 4
diff --git a/arch/arm/plat-mxc/include/mach/mvf.h b/arch/arm/plat-mxc/include/mach/mvf.h
index 028bc24cf075..ed7646beb682 100644
--- a/arch/arm/plat-mxc/include/mach/mvf.h
+++ b/arch/arm/plat-mxc/include/mach/mvf.h
@@ -103,11 +103,11 @@
  */
 #define MVF_GPIOC_BASE_ADDR		0x400FF000
 #define MVF_CPIOC_SIZE			(SZ_4K)
-#define GPIOA_BASE_ADDR     (MVF_GPIOC_BASE_ADDR + 0x0000)
-#define GPIOB_BASE_ADDR     (MVF_GPIOC_BASE_ADDR + 0x0040)
-#define GPIOC_BASE_ADDR     (MVF_GPIOC_BASE_ADDR + 0x0080)
-#define GPIOD_BASE_ADDR     (MVF_GPIOC_BASE_ADDR + 0x00c0)
-#define GPIOE_BASE_ADDR     (MVF_GPIOC_BASE_ADDR + 0x0100)
+#define GPIO0_BASE_ADDR     (MVF_GPIOC_BASE_ADDR + 0x0000)
+#define GPIO1_BASE_ADDR     (MVF_GPIOC_BASE_ADDR + 0x0040)
+#define GPIO2_BASE_ADDR     (MVF_GPIOC_BASE_ADDR + 0x0080)
+#define GPIO3_BASE_ADDR     (MVF_GPIOC_BASE_ADDR + 0x00c0)
+#define GPIO4_BASE_ADDR     (MVF_GPIOC_BASE_ADDR + 0x0100)
 
 
 /* External Serial Flash 1
@@ -206,11 +206,11 @@
 #define MVF_RLE_DEC_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x22000)
 #define MVF_QSPI0_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x24000)
 #define MVF_IOMUXC_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x28000)
-#define MVF_PORT_A_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x29000)
-#define MVF_PORT_B_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x2A000)
-#define MVF_PORT_C_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x2B000)
-#define MVF_PORT_D_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x2C000)
-#define MVF_PORT_E_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x2D000)
+#define MVF_PORT_0_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x29000)
+#define MVF_PORT_1_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x2A000)
+#define MVF_PORT_2_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x2B000)
+#define MVF_PORT_3_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x2C000)
+#define MVF_PORT_4_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x2D000)
 #define MVF_ANADIG_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x30000)
 #define MVF_SCSC_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x32000)
 #define MVF_DCU0_BASE_ADDR		(AIPS0_OFF_BASE_ADDR + 0x38000)
diff --git a/arch/arm/plat-mxc/include/mach/mvf_gpio.h b/arch/arm/plat-mxc/include/mach/mvf_gpio.h
index eedf5b2ffa76..437f1858f86f 100644
--- a/arch/arm/plat-mxc/include/mach/mvf_gpio.h
+++ b/arch/arm/plat-mxc/include/mach/mvf_gpio.h
@@ -72,11 +72,11 @@ int mvf_gpio_init(struct mvf_gpio_port*, int);
 #define GPIO_NUM(x,y)  (((x)-1)<<8 | (y))
 #define GPIO(x,y)  _PORT_PCR(x,y)<<16 | GPIO_ADDR(x,y)
 
-#define PORT_A   1
-#define PORT_B   2
-#define PORT_C   3
-#define PORT_D   4
-#define PORT_E   5
+#define PORT_0   1
+#define PORT_1   2
+#define PORT_2   3
+#define PORT_3   4
+#define PORT_4   5
 
 #define GPIO_PDOR   0x00
 #define GPIO_PSOR   0x04
diff --git a/arch/arm/plat-mxc/mvf_gpio.c b/arch/arm/plat-mxc/mvf_gpio.c
index 8ae93069446c..161653f87e3e 100644
--- a/arch/arm/plat-mxc/mvf_gpio.c
+++ b/arch/arm/plat-mxc/mvf_gpio.c
@@ -46,60 +46,60 @@ static int gpio_table_size;
  */
 //#define GTM(x,y,z) ((x<<13)|(y<<8)|((z>>2)&0x00ff))
 #define GTM(x,y,z) ((z>>2)&0x00ff)
-#define PTA  0
-#define PTB  1
-#define PTC  3
-#define PTD  4
-#define PTE  5
+#define PT0  0
+#define PT1  1
+#define PT2  2
+#define PT3  3
+#define PT4  4
 
 #define NOCFG	0
 
 static unsigned char gpio_to_mux[] = {
 	/* PT_A */
-	GTM(PTA, 0,NOCFG),GTM(PTA, 1,NOCFG),GTM(PTA, 2,NOCFG),GTM(PTA, 3,NOCFG),
-	GTM(PTA, 4,NOCFG),GTM(PTA, 5,NOCFG),GTM(PTA, 6,0x000),GTM(PTA, 7,0x218),
-	GTM(PTA, 8,0x010),GTM(PTA, 9,0x008),GTM(PTA,10,0x00c),GTM(PTA,11,0x010),
-    GTM(PTA,12,0x014),GTM(PTA,13,NOCFG),GTM(PTA,14,NOCFG),GTM(PTA,15,NOCFG),
-    GTM(PTA,16,0x018),GTM(PTA,17,0x01c),GTM(PTA,18,0x020),GTM(PTA,19,0x024),
-    GTM(PTA,20,0x028),GTM(PTA,21,0x02c),GTM(PTA,22,0x030),GTM(PTA,23,0x034),
-    GTM(PTA,24,0x038),GTM(PTA,25,0x03c),GTM(PTA,26,0x040),GTM(PTA,27,0x044),
-    GTM(PTA,28,0x048),GTM(PTA,29,0x04c),GTM(PTA,30,0x050),GTM(PTA,31,0x054),
+	GTM(PT0, 0,NOCFG),GTM(PT0, 1,NOCFG),GTM(PT0, 2,NOCFG),GTM(PT0, 3,NOCFG),
+	GTM(PT0, 4,NOCFG),GTM(PT0, 5,NOCFG),GTM(PT0, 6,0x000),GTM(PT0, 7,0x218),
+	GTM(PT0, 8,0x010),GTM(PT0, 9,0x008),GTM(PT0,10,0x00c),GTM(PT0,11,0x010),
+    GTM(PT0,12,0x014),GTM(PT0,13,NOCFG),GTM(PT0,14,NOCFG),GTM(PT0,15,NOCFG),
+    GTM(PT0,16,0x018),GTM(PT0,17,0x01c),GTM(PT0,18,0x020),GTM(PT0,19,0x024),
+    GTM(PT0,20,0x028),GTM(PT0,21,0x02c),GTM(PT0,22,0x030),GTM(PT0,23,0x034),
+    GTM(PT0,24,0x038),GTM(PT0,25,0x03c),GTM(PT0,26,0x040),GTM(PT0,27,0x044),
+    GTM(PT0,28,0x048),GTM(PT0,29,0x04c),GTM(PT0,30,0x050),GTM(PT0,31,0x054),
 	/* PT_B */
-	GTM(PTB, 0,0x058),GTM(PTB, 1,0x05c),GTM(PTB, 2,0x060),GTM(PTB, 3,0x064),
-	GTM(PTB, 4,0x068),GTM(PTB, 5,0x06c),GTM(PTB, 6,0x070),GTM(PTB, 7,0x074),
-	GTM(PTB, 8,0x078),GTM(PTB, 9,0x07c),GTM(PTB,10,0x080),GTM(PTB,11,0x084),
-    GTM(PTB,12,0x088),GTM(PTB,13,0x08c),GTM(PTB,14,0x090),GTM(PTB,15,0x094),
-    GTM(PTB,16,0x098),GTM(PTB,17,0x09c),GTM(PTB,18,0x0a0),GTM(PTB,19,0x0a4),
-    GTM(PTB,20,0x0a8),GTM(PTB,21,0x0ac),GTM(PTB,22,0x0b0),GTM(PTB,23,NOCFG),
-    GTM(PTB,24,NOCFG),GTM(PTB,25,0x17c),GTM(PTB,26,0x180),GTM(PTB,27,0x184),
-    GTM(PTB,28,0x188),GTM(PTB,29,NOCFG),GTM(PTB,30,NOCFG),GTM(PTB,31,NOCFG),
+	GTM(PT1, 0,0x058),GTM(PT1, 1,0x05c),GTM(PT1, 2,0x060),GTM(PT1, 3,0x064),
+	GTM(PT1, 4,0x068),GTM(PT1, 5,0x06c),GTM(PT1, 6,0x070),GTM(PT1, 7,0x074),
+	GTM(PT1, 8,0x078),GTM(PT1, 9,0x07c),GTM(PT1,10,0x080),GTM(PT1,11,0x084),
+    GTM(PT1,12,0x088),GTM(PT1,13,0x08c),GTM(PT1,14,0x090),GTM(PT1,15,0x094),
+    GTM(PT1,16,0x098),GTM(PT1,17,0x09c),GTM(PT1,18,0x0a0),GTM(PT1,19,0x0a4),
+    GTM(PT1,20,0x0a8),GTM(PT1,21,0x0ac),GTM(PT1,22,0x0b0),GTM(PT1,23,NOCFG),
+    GTM(PT1,24,NOCFG),GTM(PT1,25,0x17c),GTM(PT1,26,0x180),GTM(PT1,27,0x184),
+    GTM(PT1,28,0x188),GTM(PT1,29,NOCFG),GTM(PT1,30,NOCFG),GTM(PT1,31,NOCFG),
 	/* PT_C */
-	GTM(PTC, 0,0x0b4),GTM(PTC, 1,0x0b8),GTM(PTC, 2,0x0bc),GTM(PTC, 3,0x0c0),
-	GTM(PTC, 4,0x0c4),GTM(PTC, 5,0x0c8),GTM(PTC, 6,0x0cc),GTM(PTC, 7,0x0d0),
-	GTM(PTC, 8,0x0d4),GTM(PTC, 9,0x0d8),GTM(PTC,10,0x0dc),GTM(PTC,11,0x0e0),
-    GTM(PTC,12,0x0e4),GTM(PTC,13,0x0e8),GTM(PTC,14,0x0ec),GTM(PTC,15,0x0f0),
-    GTM(PTC,16,0x0f4),GTM(PTC,17,0x0f8),GTM(PTC,18,NOCFG),GTM(PTC,19,NOCFG),
-    GTM(PTC,20,NOCFG),GTM(PTC,21,NOCFG),GTM(PTC,22,NOCFG),GTM(PTC,23,NOCFG),
-    GTM(PTC,24,NOCFG),GTM(PTC,25,NOCFG),GTM(PTC,26,0x18c),GTM(PTC,27,0x190),
-    GTM(PTC,28,0x194),GTM(PTC,29,0x198),GTM(PTC,30,0x19c),GTM(PTC,31,0x1a0),
+	GTM(PT2, 0,0x0b4),GTM(PT2, 1,0x0b8),GTM(PT2, 2,0x0bc),GTM(PT2, 3,0x0c0),
+	GTM(PT2, 4,0x0c4),GTM(PT2, 5,0x0c8),GTM(PT2, 6,0x0cc),GTM(PT2, 7,0x0d0),
+	GTM(PT2, 8,0x0d4),GTM(PT2, 9,0x0d8),GTM(PT2,10,0x0dc),GTM(PT2,11,0x0e0),
+    GTM(PT2,12,0x0e4),GTM(PT2,13,0x0e8),GTM(PT2,14,0x0ec),GTM(PT2,15,0x0f0),
+    GTM(PT2,16,0x0f4),GTM(PT2,17,0x0f8),GTM(PT2,18,NOCFG),GTM(PT2,19,NOCFG),
+    GTM(PT2,20,NOCFG),GTM(PT2,21,NOCFG),GTM(PT2,22,NOCFG),GTM(PT2,23,NOCFG),
+    GTM(PT2,24,NOCFG),GTM(PT2,25,NOCFG),GTM(PT2,26,0x18c),GTM(PT2,27,0x190),
+    GTM(PT2,28,0x194),GTM(PT2,29,0x198),GTM(PT2,30,0x19c),GTM(PT2,31,0x1a0),
 	/* PT_D */
-	GTM(PTD, 0,0x13c),GTM(PTD, 1,0x140),GTM(PTD, 2,0x144),GTM(PTD, 3,0x148),
-	GTM(PTD, 4,0x14c),GTM(PTD, 5,0x150),GTM(PTD, 6,0x15c),GTM(PTD, 7,0x158),
-	GTM(PTD, 8,0x15c),GTM(PTD, 9,0x160),GTM(PTD,10,0x164),GTM(PTD,11,0x168),
-    GTM(PTD,12,0x16c),GTM(PTD,13,0x170),GTM(PTD,14,0x174),GTM(PTD,15,0x17c),
-    GTM(PTD,16,0x138),GTM(PTD,17,0x134),GTM(PTD,18,0x130),GTM(PTD,19,0x12c),
-    GTM(PTD,20,0x128),GTM(PTD,21,0x124),GTM(PTD,22,0x120),GTM(PTD,23,0x11c),
-    GTM(PTD,24,0x118),GTM(PTD,25,0x114),GTM(PTD,26,0x110),GTM(PTD,27,0x10c),
-    GTM(PTD,28,0x108),GTM(PTD,29,0x104),GTM(PTD,30,0x100),GTM(PTD,31,0x0fc),
+	GTM(PT3, 0,0x13c),GTM(PT3, 1,0x140),GTM(PT3, 2,0x144),GTM(PT3, 3,0x148),
+	GTM(PT3, 4,0x14c),GTM(PT3, 5,0x150),GTM(PT3, 6,0x15c),GTM(PT3, 7,0x158),
+	GTM(PT3, 8,0x15c),GTM(PT3, 9,0x160),GTM(PT3,10,0x164),GTM(PT3,11,0x168),
+    GTM(PT3,12,0x16c),GTM(PT3,13,0x170),GTM(PT3,14,0x174),GTM(PT3,15,0x17c),
+    GTM(PT3,16,0x138),GTM(PT3,17,0x134),GTM(PT3,18,0x130),GTM(PT3,19,0x12c),
+    GTM(PT3,20,0x128),GTM(PT3,21,0x124),GTM(PT3,22,0x120),GTM(PT3,23,0x11c),
+    GTM(PT3,24,0x118),GTM(PT3,25,0x114),GTM(PT3,26,0x110),GTM(PT3,27,0x10c),
+    GTM(PT3,28,0x108),GTM(PT3,29,0x104),GTM(PT3,30,0x100),GTM(PT3,31,0x0fc),
 	/* PT_E */
-	GTM(PTE, 0,0x1a4),GTM(PTE, 1,0x1a8),GTM(PTE, 2,0x1ac),GTM(PTE, 3,0x1b0),
-	GTM(PTE, 4,0x1b4),GTM(PTE, 5,0x1b8),GTM(PTE, 6,0x1bc),GTM(PTE, 7,0x1c0),
-	GTM(PTE, 8,0x1c4),GTM(PTE, 9,0x1c8),GTM(PTE,10,0x1cc),GTM(PTE,11,0x1d0),
-    GTM(PTE,12,0x1d4),GTM(PTE,13,0x1d8),GTM(PTE,14,0x1dc),GTM(PTE,15,0x1e0),
-    GTM(PTE,16,0x1e0),GTM(PTE,17,0x1e8),GTM(PTE,18,0x1ec),GTM(PTE,19,0x1f4),
-    GTM(PTE,20,0x1f4),GTM(PTE,21,0x1f8),GTM(PTE,22,0x1fc),GTM(PTE,23,0x200),
-    GTM(PTE,24,0x204),GTM(PTE,25,0x208),GTM(PTE,26,0x20c),GTM(PTE,27,0x210),
-    GTM(PTE,28,0x214),GTM(PTE,29,NOCFG),GTM(PTE,30,NOCFG),GTM(PTE,31,NOCFG),
+	GTM(PT4, 0,0x1a4),GTM(PT4, 1,0x1a8),GTM(PT4, 2,0x1ac),GTM(PT4, 3,0x1b0),
+	GTM(PT4, 4,0x1b4),GTM(PT4, 5,0x1b8),GTM(PT4, 6,0x1bc),GTM(PT4, 7,0x1c0),
+	GTM(PT4, 8,0x1c4),GTM(PT4, 9,0x1c8),GTM(PT4,10,0x1cc),GTM(PT4,11,0x1d0),
+    GTM(PT4,12,0x1d4),GTM(PT4,13,0x1d8),GTM(PT4,14,0x1dc),GTM(PT4,15,0x1e0),
+    GTM(PT4,16,0x1e0),GTM(PT4,17,0x1e8),GTM(PT4,18,0x1ec),GTM(PT4,19,0x1f4),
+    GTM(PT4,20,0x1f4),GTM(PT4,21,0x1f8),GTM(PT4,22,0x1fc),GTM(PT4,23,0x200),
+    GTM(PT4,24,0x204),GTM(PT4,25,0x208),GTM(PT4,26,0x20c),GTM(PT4,27,0x210),
+    GTM(PT4,28,0x214),GTM(PT4,29,NOCFG),GTM(PT4,30,NOCFG),GTM(PT4,31,NOCFG),
 };
 #define IOMUX_OFF(x) gpio_to_mux[x]
 
@@ -127,7 +127,7 @@ static struct mvf_gpio_port *mvf_gpio_ports;
  */
 
 
-/* PTx PTA to PTE */
+/* PTx PT0 to PT4 */
 #define GPIO_ODR    0x00
 #define GPIO_IDR    0x10