diff options
author | yagi <yagi@ke66.alps.lineo.co.jp> | 2012-06-18 21:42:40 +0900 |
---|---|---|
committer | Justin Waters <justin.waters@timesys.com> | 2012-07-03 17:15:17 -0400 |
commit | 36bf5ee41c11a795c5c76a5e0f0eeae484c63015 (patch) | |
tree | 0affba19b9c466906b8303e6005deb762657a38a | |
parent | 60bd1cf3d0c6cf4c0470ee1db28d93eb8e47c1c1 (diff) |
update: change PIT to Global Timer.
-rw-r--r-- | arch/arm/include/asm/entry-macro-multi.S | 7 | ||||
-rw-r--r-- | arch/arm/include/asm/hardware/entry-macro-gic.S | 11 | ||||
-rw-r--r-- | arch/arm/mach-mvf/clock.c | 19 | ||||
-rw-r--r-- | arch/arm/mach-mvf/irq.c | 9 | ||||
-rw-r--r-- | arch/arm/plat-mxc/mvf_time.c | 423 |
5 files changed, 183 insertions, 286 deletions
diff --git a/arch/arm/include/asm/entry-macro-multi.S b/arch/arm/include/asm/entry-macro-multi.S index 2da8547de6d6..459d47f60962 100644 --- a/arch/arm/include/asm/entry-macro-multi.S +++ b/arch/arm/include/asm/entry-macro-multi.S @@ -33,6 +33,13 @@ bne do_local_timer #endif #endif + +#ifdef CONFIG_ARCH_MVF /* MVF Global Timer Support*/ + test_for_gtirq r0, r6, r5, lr + movne r0, sp + adrne lr, BSYM(1b) + bne do_global_timer +#endif 9997: .endm diff --git a/arch/arm/include/asm/hardware/entry-macro-gic.S b/arch/arm/include/asm/hardware/entry-macro-gic.S index c115b82fe80a..6cf181a64dc9 100644 --- a/arch/arm/include/asm/hardware/entry-macro-gic.S +++ b/arch/arm/include/asm/hardware/entry-macro-gic.S @@ -73,3 +73,14 @@ streq \irqstat, [\base, #GIC_CPU_EOI] cmp \tmp, #0 .endm + +#ifdef CONFIG_ARCH_MVF /* MVF Global Timer Support*/ + .macro test_for_gtirq, irqnr, irqstat, base, tmp + bic \irqnr, \irqstat, #0x1c00 + mov \tmp, #0 + cmp \irqnr, #27 + moveq \tmp, #1 + streq \irqstat, [\base, #GIC_CPU_EOI] + cmp \tmp, #0 + .endm +#endif diff --git a/arch/arm/mach-mvf/clock.c b/arch/arm/mach-mvf/clock.c index cf5e4a2cc88a..fdd0c2c05cb1 100644 --- a/arch/arm/mach-mvf/clock.c +++ b/arch/arm/mach-mvf/clock.c @@ -3072,6 +3072,16 @@ static struct clk trace_clk = { .set_parent = _clk_trace_set_parent, }; +static struct clk ca5_scu_clk = { + __INIT_CLK_DEBUG(ca5_scu_clk) + .parent = &plat_bus_clk, +}; + +static struct clk twd_clk = { + __INIT_CLK_DEBUG(twd_clk) + .parent = &ca5_scu_clk, +}; + static struct clk dma_mux0_clk = { __INIT_CLK_DEBUG(dma_mux0_clk) .parent = &ips_bus_clk, @@ -3804,6 +3814,8 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK(NULL, "gpu_clk", gpu_clk), _REGISTER_CLOCK(NULL, "swo_clk", swo_clk), _REGISTER_CLOCK(NULL, "trace_clk", trace_clk), + _REGISTER_CLOCK(NULL, "ca5_scu_clk", ca5_scu_clk), + _REGISTER_CLOCK("smp_twd", NULL, twd_clk), _REGISTER_CLOCK(NULL, "dma_mix0_clk", dma_mux0_clk), _REGISTER_CLOCK(NULL, "dma_mix1_clk", dma_mux1_clk), _REGISTER_CLOCK("mvf-uart.0", NULL, uart0_clk), @@ -4250,14 +4262,11 @@ int __init mvf_clocks_init(unsigned long sirc, unsigned long firc, 3 << MXC_CCM_CCGRx_CG8_OFFSET, MXC_CCM_CCGR11); -#if 1 //FIXME - base = ioremap(MVF_PIT_BASE_ADDR, SZ_4K); - mvf_timer_init(&pit_clk, base, MXC_INT_PIT); -#endif + base = MVF_IO_ADDRESS(MVF_CA5_SCU_GIC_BASE_ADDR + 0x200); + mvf_timer_init(&ca5_scu_clk, base, IRQ_GLOBALTIMER); lp_high_freq = 0; lp_med_freq = 0; return 0; - } diff --git a/arch/arm/mach-mvf/irq.c b/arch/arm/mach-mvf/irq.c index 45653fe10cde..ac0a07240512 100644 --- a/arch/arm/mach-mvf/irq.c +++ b/arch/arm/mach-mvf/irq.c @@ -62,16 +62,15 @@ void mvf_init_irq(void) __raw_writew(0x01,mscm_base + 0x880 + (i<<1)); } - /* start offset if private timer irq id, which is 29. + /* start offset if global timer irq id, which is 27. * ID table: * Global timer, PPI -> ID27 - * A legacy nFIQ, PPI -> ID28 - * Private timer, PPI -> ID29 + * Private(Local) timer, PPI -> ID29 * Watchdog timers, PPI -> ID30 * A legacy nIRQ, PPI -> ID31 */ - gic_init(0, 29, MVF_IO_ADDRESS(MVF_CA5_INTD_BASE_ADDR), - MVF_IO_ADDRESS(MVF_CA5_SCU_GIC_BASE_ADDR + 0x100)); //FIXME + gic_init(0, 27, MVF_IO_ADDRESS(MVF_CA5_INTD_BASE_ADDR), + MVF_IO_ADDRESS(MVF_CA5_SCU_GIC_BASE_ADDR + 0x100)); #if 0 if (enable_wait_mode) { diff --git a/arch/arm/plat-mxc/mvf_time.c b/arch/arm/plat-mxc/mvf_time.c index 07c7b6e248fc..eb012a140d23 100644 --- a/arch/arm/plat-mxc/mvf_time.c +++ b/arch/arm/plat-mxc/mvf_time.c @@ -1,350 +1,221 @@ /* - * based on linux/arch/arm/plat-mxc/time.c + * arch/armplat-mxc/mvf_time.c * - * Copyright (C) 2000-2001 Deep Blue Solutions - * Copyright (C) 2002 Shane Nay (shane@minirl.com) - * Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com) - * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) + * based on linux/arch/arm/kernel/smp_twd.c * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * Copyright (C) 2002 ARM Ltd. + * All Rights Reserved * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. */ - +#include <linux/clockchips.h> #include <linux/interrupt.h> #include <linux/irq.h> -#include <linux/clockchips.h> +#include <linux/io.h> #include <linux/clk.h> -#include <linux/time.h> -#include <linux/timer.h> -#include <linux/timex.h> -#include <linux/profile.h> -#include <linux/sched.h> - +#include <linux/cpufreq.h> +#include <linux/err.h> -#include <mach/hardware.h> #include <asm/sched_clock.h> -#include <asm/mach/time.h> -#include <mach/common.h> - -/* - * VF Timer: using Periodic Interrupt Timer(PIT) - */ -/* PIT clock has a frequency of 50MHz(20ns/clock) */ -#define BASE_CLOCK 50000000 -#define TIMER_CH 0 - -/* defines common for VF All chanels */ -#define PIT_MCR 0x0000 -#define PIT_MCR_MDIS (1<<1) - -#define PIT_LTMR64H 0x00e0 -#define PIT_LTMR64L 0x00e4 - -/* */ -#define PIT_LDVAL(x) 0x100+(x<<4) -#define PIT_CVAL(x) 0x104+(x<<4) -#define PIT_TCTRL(x) 0x108+(x<<4) -#define PIT_TCTRL_CHN (1<<2) /* Chain Mode */ -#define PIT_TCTRL_TIE (1<<1) /* Timer Interrupt Enable */ -#define PIT_TCTRL_TEN (1<<0) /* Timer Enable */ -#define PIT_TFLG(x) 0x10C+(x<<4) -#define PIT_TFLG_TIF (1<<0) - - +#include <asm/hardware/gic.h> +#include <mach/hardware.h> +/* global timer registers */ +#define GT_COUNT_LOWER 0x0 +#define GT_COUNT_UPPER 0x4 +#define GT_CNTRL 0x8 +#define GT_CNTRL_AOUT_INC (1 << 3) +#define GT_CNTRL_INT_EN (1 << 2) +#define GT_CNTRL_CMP_EN (1 << 1) +#define GT_CNTRL_TIMER_EN (1 << 0) +#define GT_INT_STAT 0xC +#define GT_INT_STAT_EFLG (1 << 0) +#define GT_CMP_LOWER 0x10 +#define GT_CMP_UPPER 0x14 +#define GT_AUTO_INC 0x18 + +/* set up by the platform code */ +void __iomem *timer_base; +static unsigned long timer_rate; +static struct clocksource clocksource_mvf; static struct clock_event_device clockevent_mvf; -static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED; -static unsigned long ticks_per_jiffy; - -static void __iomem *timer_base; -static inline void gpt_irq_disable(void) -{ - unsigned int tmp; - - printk("%s[%d]:j = %ld\n",__func__,__LINE__,jiffies); - tmp = __raw_readl(timer_base + PIT_TCTRL(TIMER_CH)); - __raw_writel(tmp & ~PIT_TCTRL_TIE , timer_base + PIT_TCTRL(TIMER_CH)); -} +static DEFINE_CLOCK_DATA(cd); -static inline void gpt_irq_enable(void) +static cycle_t mvf_clock_source_read(struct clocksource *c) { - unsigned int tmp; + cycle_t upper, val; + + while (1) { + upper = __raw_readl(timer_base + GT_COUNT_UPPER); + val = __raw_readl(timer_base + GT_COUNT_LOWER); + if (upper == __raw_readl(timer_base + GT_COUNT_UPPER)) { + val |= upper << 32; + break; + } + } - printk("%s[%d]:j = %ld\n",__func__,__LINE__,jiffies); - tmp = __raw_readl(timer_base + PIT_TCTRL(TIMER_CH)); - __raw_writel(tmp | PIT_TCTRL_TIE , timer_base + PIT_TCTRL(TIMER_CH)); + return val; } -static void gpt_irq_acknowledge(void) +static void notrace mvf_update_sched_clock(void) { - - __raw_writel(__raw_readl(timer_base + PIT_TFLG(TIMER_CH)), - timer_base + PIT_TFLG(TIMER_CH)); + cycle_t cyc = mvf_clock_source_read(&clocksource_mvf); + update_sched_clock(&cd, cyc, (u32)~0); } -static void __iomem *sched_clock_reg; -static void __iomem *sched_clock_ld; +static struct clocksource clocksource_mvf = { + .name = "mvf_timer", + .rating = 350, + .read = mvf_clock_source_read, + .mask = CLOCKSOURCE_MASK(64), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; -static DEFINE_CLOCK_DATA(cd); -unsigned long long notrace sched_clock(void) +static void mvf_timer_clear_int(void) { - cycle_t cyc = sched_clock_reg ? ((u32)~0 - - __raw_readl(sched_clock_reg)) : 0; - return cyc_to_sched_clock(&cd, cyc, (u32)~0); + if (__raw_readl(timer_base + GT_INT_STAT)) { + __raw_writel(GT_INT_STAT_EFLG, timer_base + GT_INT_STAT); + } } -static void notrace mvf_update_sched_clock(void) +static void mvf_set_mode(enum clock_event_mode mode, + struct clock_event_device *clk) { - cycle_t cyc = sched_clock_reg ? ((u32)~0 - - __raw_readl(sched_clock_reg)) : 0; - update_sched_clock(&cd, cyc, (u32)~0); -} + unsigned long ctrl; + cycle_t cmp; + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + cmp = mvf_clock_source_read(&clocksource_mvf) + (timer_rate / HZ); + __raw_writel((u32)(cmp & 0xFFFFFFFF), timer_base + GT_CMP_LOWER); + __raw_writel((u32)(cmp >> 32), timer_base + GT_CMP_UPPER); + __raw_writel(timer_rate / HZ, timer_base + GT_AUTO_INC); + /* timer load already set up */ + ctrl = GT_CNTRL_TIMER_EN | GT_CNTRL_CMP_EN | GT_CNTRL_INT_EN | + GT_CNTRL_AOUT_INC; + gic_enable_ppi(clk->irq); + mvf_timer_clear_int(); + break; + case CLOCK_EVT_MODE_ONESHOT: + /* period set, and timer enabled in 'next_event' hook */ + ctrl = GT_CNTRL_CMP_EN | GT_CNTRL_INT_EN; + gic_enable_ppi(clk->irq); + mvf_timer_clear_int(); + break; + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_SHUTDOWN: + default: + ctrl = 0; + gic_disable_ppi(clk->irq); + } -cycle_t clocksource_mmio_readl_pit(struct clocksource *c) -{ - cycle_t cyc; - cyc = __raw_readl(timer_base + PIT_LDVAL(TIMER_CH)) - - __raw_readl(timer_base + PIT_CVAL(TIMER_CH)); - - return cyc; + __raw_writel(ctrl, timer_base + GT_CNTRL); } -static int __init mvf_clocksource_init(struct clk *timer_clk) +static int mvf_set_next_event(unsigned long evt, + struct clock_event_device *unused) { - unsigned int c = clk_get_rate(timer_clk); - void __iomem *reg = timer_base + PIT_CVAL(TIMER_CH); + unsigned long ctrl = __raw_readl(timer_base + GT_CNTRL); + cycle_t cmp = mvf_clock_source_read(&clocksource_mvf); - sched_clock_reg = reg; - sched_clock_ld = timer_base + PIT_LDVAL(TIMER_CH); - ticks_per_jiffy = DIV_ROUND_CLOSEST(c,HZ); + ctrl |= GT_CNTRL_TIMER_EN; + cmp += (cycle_t)evt; + + __raw_writel((u32)(cmp & 0xFFFFFFFF), timer_base + GT_CMP_LOWER); + __raw_writel((u32)(cmp >> 32), timer_base + GT_CMP_UPPER); + __raw_writel(ctrl, timer_base + GT_CNTRL); - init_sched_clock(&cd, mvf_update_sched_clock, 32, c); -#if 1 -#if 0 - return clocksource_mmio_init(reg, "mvf_timer1", c, 200, 32, - clocksource_mmio_readl_down); -#else - return clocksource_mmio_init(reg, "mvf_timer1", c, 200, 32, - clocksource_mmio_readl_pit); -#endif -#else return 0; -#endif } - - -static void mvf_set_mode(enum clock_event_mode mode, - struct clock_event_device *evt) +#if 1 +asmlinkage void __exception_irq_entry do_global_timer(struct pt_regs *regs) { - unsigned long flags; - - /* - * The timer interrupt generation is disabled at least - * for enough time to call mvf_set_next_event() - */ - - local_irq_save(flags); - - /* Disable interrupt in GPT module */ - gpt_irq_disable(); + struct pt_regs *old_regs = set_irq_regs(regs); + struct clock_event_device *evt = &clockevent_mvf; + u32 reg; - if (mode != clockevent_mode) { - /* Clear pending interrupt */ - gpt_irq_acknowledge(); + reg = __raw_readl(timer_base + GT_INT_STAT); + if (reg) { + mvf_timer_clear_int(); + evt->event_handler(evt); } - -#ifdef DEBUG - printk(KERN_INFO "mvf_set_mode: changing mode from %s to %s\n", - clock_event_mode_label[clockevent_mode], - clock_event_mode_label[mode]); -#endif /* DEBUG */ - /* Remember timer mode */ - clockevent_mode = mode; - local_irq_restore(flags); + set_irq_regs(old_regs); - switch (mode) { - case CLOCK_EVT_MODE_PERIODIC: - local_irq_save(flags); - gpt_irq_enable(); - local_irq_restore(flags); -#if 0 - printk(KERN_ERR"mvf_set_mode: Periodic mode is not " - "supported for MVF\n"); -#endif - break; - case CLOCK_EVT_MODE_ONESHOT: - /* - * Do not put overhead of interrupt enable/disable into - * mvf_set_next_event(), the core has about 4 minutes - * to call mvf_set_next_event() or shutdown clock after - * mode switching - */ - local_irq_save(flags); - gpt_irq_enable(); - local_irq_restore(flags); - break; - case CLOCK_EVT_MODE_SHUTDOWN: - case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_RESUME: - /* Left event sources disabled, no more interrupts appear */ - break; - } - /* DEBUG */ printk("DBG: %s[%d]: Start[%d] jiffies = %ld\n",__func__,__LINE__,mode, jiffies); } - -/* - * IRQ handler for the timer - */ - +#else static irqreturn_t mvf_timer_interrupt(int irq, void *dev_id) { struct clock_event_device *evt = &clockevent_mvf; - uint32_t tstat; - unsigned long reg; + u32 reg; - // printk("%s[%d]:j = %ld\n",__func__,__LINE__,jiffies); - tstat = __raw_readl(timer_base + PIT_TFLG(TIMER_CH)); - if ( tstat ) { - __raw_writel(tstat, timer_base + PIT_TFLG(TIMER_CH)); - gpt_irq_acknowledge(); -#if 1 + reg = __raw_readl(timer_base + GT_INT_STAT); + if (reg) { + mvf_timer_clear_int(); evt->event_handler(evt); -#else - xtime_update(1); -#endif return IRQ_HANDLED; } return IRQ_NONE; } -static int mvf_set_next_event(unsigned long evt, - struct clock_event_device *unused) -{ -#if 1 - unsigned long tcmp; - tcmp = __raw_readl(timer_base + PIT_CVAL(TIMER_CH)); - /* STOP Time */ - __raw_writel(__raw_readl(timer_base + PIT_TCTRL(TIMER_CH)) - & ~(PIT_TCTRL_TEN), - timer_base + PIT_TCTRL(TIMER_CH)); - __raw_writel(tcmp - evt, timer_base + PIT_LDVAL(TIMER_CH)); - __raw_writel(evt, timer_base + PIT_LDVAL(TIMER_CH)); - /* Start Timer */ - __raw_writel(__raw_readl(timer_base + PIT_TCTRL(TIMER_CH)) - | (PIT_TCTRL_TEN), - timer_base + PIT_TCTRL(TIMER_CH)); - // printk("tcmp = %ld, evt = %ld\n",tcmp,evt); -#else - unsigned long tcmp,cval; - unsigned long oval,nval; - tcmp = evt; - cval = __raw_readl(timer_base + PIT_CVAL(TIMER_CH)); - oval = __raw_readl(timer_base + PIT_LDVAL(TIMER_CH)); - /* STOP Time */ - __raw_writel(__raw_readl(timer_base + PIT_TCTRL(TIMER_CH)) - & ~(PIT_TCTRL_TEN), - timer_base + PIT_TCTRL(TIMER_CH)); - __raw_writel(tcmp, timer_base + PIT_LDVAL(TIMER_CH)); - /* Start Timer */ - __raw_writel(__raw_readl(timer_base + PIT_TCTRL(TIMER_CH)) - | (PIT_TCTRL_TEN), - timer_base + PIT_TCTRL(TIMER_CH)); - - __raw_writel(tcmp+cval, timer_base + PIT_LDVAL(TIMER_CH)); - nval = __raw_readl(timer_base + PIT_LDVAL(TIMER_CH)); - tcmp = __raw_readl(timer_base + PIT_CVAL(TIMER_CH)); - // printk("DEBUG: KATSU: evt=%lud, oldval = %lud, nval = %lud,cval = %lud,tcmp = %lud\n",evt,oval,nval,cval,tcmp); -#endif - return 0; - -} - - - static struct irqaction mvf_timer_irq = { .name = "MVF Timer Tick", .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, .handler = mvf_timer_interrupt, }; +#endif static struct clock_event_device clockevent_mvf = { - .name = "mvf_timer1", - .features = CLOCK_EVT_FEAT_PERIODIC, - // .features = CLOCK_EVT_FEAT_ONESHOT, - .shift = 32, + .name = "mvf_timer", + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, //FIXME + //.shift = 32, //FIXME .set_mode = mvf_set_mode, .set_next_event = mvf_set_next_event, - .rating = 200, + .rating = 350, //FIXME }; -static int __init mvf_clockevent_init(struct clk *timer_clk) -{ - unsigned int c = clk_get_rate(timer_clk); - - clockevent_mvf.mult = div_sc(c, NSEC_PER_SEC, - clockevent_mvf.shift); - clockevent_mvf.max_delta_ns = - clockevent_delta2ns(0xfffffffe, &clockevent_mvf); - clockevent_mvf.min_delta_ns = - clockevent_delta2ns(0xff, &clockevent_mvf); - - clockevent_mvf.cpumask = cpumask_of(0); - - clockevents_register_device(&clockevent_mvf); - - return 0; -} - +/* + * Setup the global clock events for a CPU. + */ void __init mvf_timer_init(struct clk *timer_clk, void __iomem *base, int irq) { - -#if 1 /* Clock is fix to 50MHz */ clk_enable(timer_clk); -#endif - // printk("PIT base = 0x%08lx",(unsigned long)base); + timer_base = base; /* - * Initialise to a known state (all timers off, and timing reset) + * init timer */ + /* stop timer */ + __raw_writel(0, timer_base + GT_CNTRL); + /* clear timer count */ + __raw_writel(0, timer_base + GT_COUNT_LOWER); + __raw_writel(0, timer_base + GT_COUNT_UPPER); + /* clear timer int */ + mvf_timer_clear_int(); + /* clear timer cmp val */ + __raw_writel(0, timer_base + GT_CMP_LOWER); + __raw_writel(0, timer_base + GT_CMP_UPPER); + /* clear auto increment val */ + __raw_writel(0, timer_base + GT_AUTO_INC); + + timer_rate = clk_get_rate(timer_clk); + init_sched_clock(&cd, mvf_update_sched_clock, 64, timer_rate); + clocksource_register_hz(&clocksource_mvf, timer_rate); + clockevent_mvf.irq = irq; + clockevent_mvf.cpumask = cpumask_of(0); + clockevents_config_and_register(&clockevent_mvf, timer_rate, + 0xf, 0xffffffff); - // __raw_writel(PIT_MCR_MDIS, timer_base + PIT_MCR); /* Stop PIT */ - __raw_writel(0, timer_base + PIT_MCR); /* Stop PIT */ - - /* init and register the timer to the framework */ - mvf_clocksource_init(timer_clk); - mvf_clockevent_init(timer_clk); - - /* Make irqs happen */ + /* Make sure our local interrupt controller has this enabled */ +#if 1 + gic_enable_ppi(irq); +#else setup_irq(irq, &mvf_timer_irq); - - /* STOP Time */ - __raw_writel(__raw_readl(timer_base + PIT_TCTRL(TIMER_CH)) - & ~(PIT_TCTRL_TEN), - timer_base + PIT_TCTRL(TIMER_CH)); - - __raw_writel(ticks_per_jiffy, timer_base + PIT_LDVAL(TIMER_CH)); - gpt_irq_enable(); - /* Start Timer */ - __raw_writel(__raw_readl(timer_base + PIT_TCTRL(TIMER_CH)) - | (PIT_TCTRL_TEN), - timer_base + PIT_TCTRL(TIMER_CH)); - - +#endif } |