From 5d9c3b547f501fad7d59147d3b7acc99b4ec4afd Mon Sep 17 00:00:00 2001 From: Bhuvanchandra DV Date: Wed, 5 Oct 2016 16:57:23 +0530 Subject: examples: vf6xx_colibri_m4: Add GPIO iomux support Add support to mux GPIO pin during GPIO init. Signed-off-by: Bhuvanchandra DV Signed-off-by: Stefan Agner --- examples/vf6xx_colibri_m4/pin_mux.c | 8 ++ examples/vf6xx_colibri_m4/pin_mux.h | 152 ++++++++++++++++++++++++++++++++++++ platform/drivers/inc/gpio_vf6xx.h | 139 +-------------------------------- platform/drivers/src/gpio_vf6xx.c | 2 + 4 files changed, 163 insertions(+), 138 deletions(-) diff --git a/examples/vf6xx_colibri_m4/pin_mux.c b/examples/vf6xx_colibri_m4/pin_mux.c index 508facd..df9a28e 100644 --- a/examples/vf6xx_colibri_m4/pin_mux.c +++ b/examples/vf6xx_colibri_m4/pin_mux.c @@ -39,6 +39,14 @@ #include "device_imx.h" #include "pin_mux.h" +void configure_gpio_pin(uint32_t gpio) +{ + uint32_t iomux_addr = iomux_gpio_pad_addr[gpio]; + + *((volatile uint32_t *)((uint32_t)iomux_addr)) = ((IOMUXC_MUX_MODE_ALT0) << IOMUXC_MUX_MODE_SHIFT | (IOMUXC_SPEED_MEDIUM) << IOMUXC_SPEED_SHIFT | + (IOMUXC_DSE_50OHM) << IOMUXC_DSE_SHIFT | (IOMUXC_PUS_PU_47KOHM) << IOMUXC_PUS_SHIFT); +} + void configure_uart_pins(UART_Type* base) { switch((uint32_t)base) diff --git a/examples/vf6xx_colibri_m4/pin_mux.h b/examples/vf6xx_colibri_m4/pin_mux.h index 2155950..ca80bfc 100644 --- a/examples/vf6xx_colibri_m4/pin_mux.h +++ b/examples/vf6xx_colibri_m4/pin_mux.h @@ -41,6 +41,158 @@ #include "device_imx.h" +uint32_t iomux_gpio_pad_addr[] = { + (uint32_t)(&IOMUXC_PTA6), + (uint32_t)(&IOMUXC_PTA8), + (uint32_t)(&IOMUXC_PTA9), + (uint32_t)(&IOMUXC_PTA10), + (uint32_t)(&IOMUXC_PTA11), + (uint32_t)(&IOMUXC_PTA12), + (uint32_t)(&IOMUXC_PTA16), + (uint32_t)(&IOMUXC_PTA17), + (uint32_t)(&IOMUXC_PTA18), + (uint32_t)(&IOMUXC_PTA19), + (uint32_t)(&IOMUXC_PTA20), + (uint32_t)(&IOMUXC_PTA21), + (uint32_t)(&IOMUXC_PTA22), + (uint32_t)(&IOMUXC_PTA23), + (uint32_t)(&IOMUXC_PTA24), + (uint32_t)(&IOMUXC_PTA25), + (uint32_t)(&IOMUXC_PTA26), + (uint32_t)(&IOMUXC_PTA27), + (uint32_t)(&IOMUXC_PTA28), + (uint32_t)(&IOMUXC_PTA29), + (uint32_t)(&IOMUXC_PTA30), + (uint32_t)(&IOMUXC_PTA31), + (uint32_t)(&IOMUXC_PTB0), + (uint32_t)(&IOMUXC_PTB1), + (uint32_t)(&IOMUXC_PTB2), + (uint32_t)(&IOMUXC_PTB3), + (uint32_t)(&IOMUXC_PTB4), + (uint32_t)(&IOMUXC_PTB5), + (uint32_t)(&IOMUXC_PTB6), + (uint32_t)(&IOMUXC_PTB7), + (uint32_t)(&IOMUXC_PTB8), + (uint32_t)(&IOMUXC_PTB9), + (uint32_t)(&IOMUXC_PTB10), + (uint32_t)(&IOMUXC_PTB11), + (uint32_t)(&IOMUXC_PTB12), + (uint32_t)(&IOMUXC_PTB13), + (uint32_t)(&IOMUXC_PTB14), + (uint32_t)(&IOMUXC_PTB15), + (uint32_t)(&IOMUXC_PTB16), + (uint32_t)(&IOMUXC_PTB17), + (uint32_t)(&IOMUXC_PTB18), + (uint32_t)(&IOMUXC_PTB19), + (uint32_t)(&IOMUXC_PTB20), + (uint32_t)(&IOMUXC_PTB21), + (uint32_t)(&IOMUXC_PTB22), + (uint32_t)(&IOMUXC_PTC0), + (uint32_t)(&IOMUXC_PTC1), + (uint32_t)(&IOMUXC_PTC2), + (uint32_t)(&IOMUXC_PTC3), + (uint32_t)(&IOMUXC_PTC4), + (uint32_t)(&IOMUXC_PTC5), + (uint32_t)(&IOMUXC_PTC6), + (uint32_t)(&IOMUXC_PTC7), + (uint32_t)(&IOMUXC_PTC8), + (uint32_t)(&IOMUXC_PTC9), + (uint32_t)(&IOMUXC_PTC10), + (uint32_t)(&IOMUXC_PTC11), + (uint32_t)(&IOMUXC_PTC12), + (uint32_t)(&IOMUXC_PTC13), + (uint32_t)(&IOMUXC_PTC14), + (uint32_t)(&IOMUXC_PTC15), + (uint32_t)(&IOMUXC_PTC16), + (uint32_t)(&IOMUXC_PTC17), + (uint32_t)(&IOMUXC_PTD31), + (uint32_t)(&IOMUXC_PTD30), + (uint32_t)(&IOMUXC_PTD29), + (uint32_t)(&IOMUXC_PTD28), + (uint32_t)(&IOMUXC_PTD27), + (uint32_t)(&IOMUXC_PTD26), + (uint32_t)(&IOMUXC_PTD25), + (uint32_t)(&IOMUXC_PTD24), + (uint32_t)(&IOMUXC_PTD23), + (uint32_t)(&IOMUXC_PTD22), + (uint32_t)(&IOMUXC_PTD21), + (uint32_t)(&IOMUXC_PTD20), + (uint32_t)(&IOMUXC_PTD19), + (uint32_t)(&IOMUXC_PTD18), + (uint32_t)(&IOMUXC_PTD17), + (uint32_t)(&IOMUXC_PTD16), + (uint32_t)(&IOMUXC_PTD0), + (uint32_t)(&IOMUXC_PTD1), + (uint32_t)(&IOMUXC_PTD2), + (uint32_t)(&IOMUXC_PTD3), + (uint32_t)(&IOMUXC_PTD4), + (uint32_t)(&IOMUXC_PTD5), + (uint32_t)(&IOMUXC_PTD6), + (uint32_t)(&IOMUXC_PTD7), + (uint32_t)(&IOMUXC_PTD8), + (uint32_t)(&IOMUXC_PTD9), + (uint32_t)(&IOMUXC_PTD10), + (uint32_t)(&IOMUXC_PTD11), + (uint32_t)(&IOMUXC_PTD12), + (uint32_t)(&IOMUXC_PTD13), + (uint32_t)(&IOMUXC_PTB23), + (uint32_t)(&IOMUXC_PTB24), + (uint32_t)(&IOMUXC_PTB25), + (uint32_t)(&IOMUXC_PTB26), + (uint32_t)(&IOMUXC_PTB27), + (uint32_t)(&IOMUXC_PTB28), + (uint32_t)(&IOMUXC_PTC26), + (uint32_t)(&IOMUXC_PTC27), + (uint32_t)(&IOMUXC_PTC28), + (uint32_t)(&IOMUXC_PTC29), + (uint32_t)(&IOMUXC_PTC30), + (uint32_t)(&IOMUXC_PTC31), + (uint32_t)(&IOMUXC_PTE0), + (uint32_t)(&IOMUXC_PTE1), + (uint32_t)(&IOMUXC_PTE2), + (uint32_t)(&IOMUXC_PTE3), + (uint32_t)(&IOMUXC_PTE4), + (uint32_t)(&IOMUXC_PTE5), + (uint32_t)(&IOMUXC_PTE6), + (uint32_t)(&IOMUXC_PTE7), + (uint32_t)(&IOMUXC_PTE8), + (uint32_t)(&IOMUXC_PTE9), + (uint32_t)(&IOMUXC_PTE10), + (uint32_t)(&IOMUXC_PTE11), + (uint32_t)(&IOMUXC_PTE12), + (uint32_t)(&IOMUXC_PTE13), + (uint32_t)(&IOMUXC_PTE14), + (uint32_t)(&IOMUXC_PTE15), + (uint32_t)(&IOMUXC_PTE16), + (uint32_t)(&IOMUXC_PTE17), + (uint32_t)(&IOMUXC_PTE18), + (uint32_t)(&IOMUXC_PTE19), + (uint32_t)(&IOMUXC_PTE20), + (uint32_t)(&IOMUXC_PTE21), + (uint32_t)(&IOMUXC_PTE22), + (uint32_t)(&IOMUXC_PTE23), + (uint32_t)(&IOMUXC_PTE24), + (uint32_t)(&IOMUXC_PTE25), + (uint32_t)(&IOMUXC_PTE26), + (uint32_t)(&IOMUXC_PTE27), + (uint32_t)(&IOMUXC_PTE28), + (uint32_t)(&IOMUXC_PTA7), +}; + +/* +** =================================================================== +** Method : pin_mux_GPIO (component PinSettings) +*/ +/*! +** @brief +** GPIO method sets registers according routing settings. Call +** this method code to route desired pin as GPIO +** @param +** uint32_t gpio - gpio number 0-135 +*/ +/* ===================================================================*/ +void configure_gpio_pin(uint32_t gpio); + /* ** =================================================================== ** Method : pin_mux_UART (component PinSettings) diff --git a/platform/drivers/inc/gpio_vf6xx.h b/platform/drivers/inc/gpio_vf6xx.h index d729598..e420b84 100644 --- a/platform/drivers/inc/gpio_vf6xx.h +++ b/platform/drivers/inc/gpio_vf6xx.h @@ -35,6 +35,7 @@ #include #include #include "device_imx.h" +#include "pin_mux.h" /*! * @addtogroup gpio_driver @@ -64,144 +65,6 @@ typedef struct GpioInit gpio_pin_direction_t direction; /*!< Specifies the pin direction. */ } gpio_init_t; -uint32_t iomux_gpio_pad_addr[] = { - (uint32_t)(&IOMUXC_PTA6), - (uint32_t)(&IOMUXC_PTA8), - (uint32_t)(&IOMUXC_PTA9), - (uint32_t)(&IOMUXC_PTA10), - (uint32_t)(&IOMUXC_PTA11), - (uint32_t)(&IOMUXC_PTA12), - (uint32_t)(&IOMUXC_PTA16), - (uint32_t)(&IOMUXC_PTA17), - (uint32_t)(&IOMUXC_PTA18), - (uint32_t)(&IOMUXC_PTA19), - (uint32_t)(&IOMUXC_PTA20), - (uint32_t)(&IOMUXC_PTA21), - (uint32_t)(&IOMUXC_PTA22), - (uint32_t)(&IOMUXC_PTA23), - (uint32_t)(&IOMUXC_PTA24), - (uint32_t)(&IOMUXC_PTA25), - (uint32_t)(&IOMUXC_PTA26), - (uint32_t)(&IOMUXC_PTA27), - (uint32_t)(&IOMUXC_PTA28), - (uint32_t)(&IOMUXC_PTA29), - (uint32_t)(&IOMUXC_PTA30), - (uint32_t)(&IOMUXC_PTA31), - (uint32_t)(&IOMUXC_PTB0), - (uint32_t)(&IOMUXC_PTB1), - (uint32_t)(&IOMUXC_PTB2), - (uint32_t)(&IOMUXC_PTB3), - (uint32_t)(&IOMUXC_PTB4), - (uint32_t)(&IOMUXC_PTB5), - (uint32_t)(&IOMUXC_PTB6), - (uint32_t)(&IOMUXC_PTB7), - (uint32_t)(&IOMUXC_PTB8), - (uint32_t)(&IOMUXC_PTB9), - (uint32_t)(&IOMUXC_PTB10), - (uint32_t)(&IOMUXC_PTB11), - (uint32_t)(&IOMUXC_PTB12), - (uint32_t)(&IOMUXC_PTB13), - (uint32_t)(&IOMUXC_PTB14), - (uint32_t)(&IOMUXC_PTB15), - (uint32_t)(&IOMUXC_PTB16), - (uint32_t)(&IOMUXC_PTB17), - (uint32_t)(&IOMUXC_PTB18), - (uint32_t)(&IOMUXC_PTB19), - (uint32_t)(&IOMUXC_PTB20), - (uint32_t)(&IOMUXC_PTB21), - (uint32_t)(&IOMUXC_PTB22), - (uint32_t)(&IOMUXC_PTC0), - (uint32_t)(&IOMUXC_PTC1), - (uint32_t)(&IOMUXC_PTC2), - (uint32_t)(&IOMUXC_PTC3), - (uint32_t)(&IOMUXC_PTC4), - (uint32_t)(&IOMUXC_PTC5), - (uint32_t)(&IOMUXC_PTC6), - (uint32_t)(&IOMUXC_PTC7), - (uint32_t)(&IOMUXC_PTC8), - (uint32_t)(&IOMUXC_PTC9), - (uint32_t)(&IOMUXC_PTC10), - (uint32_t)(&IOMUXC_PTC11), - (uint32_t)(&IOMUXC_PTC12), - (uint32_t)(&IOMUXC_PTC13), - (uint32_t)(&IOMUXC_PTC14), - (uint32_t)(&IOMUXC_PTC15), - (uint32_t)(&IOMUXC_PTC16), - (uint32_t)(&IOMUXC_PTC17), - (uint32_t)(&IOMUXC_PTD31), - (uint32_t)(&IOMUXC_PTD30), - (uint32_t)(&IOMUXC_PTD29), - (uint32_t)(&IOMUXC_PTD28), - (uint32_t)(&IOMUXC_PTD27), - (uint32_t)(&IOMUXC_PTD26), - (uint32_t)(&IOMUXC_PTD25), - (uint32_t)(&IOMUXC_PTD24), - (uint32_t)(&IOMUXC_PTD23), - (uint32_t)(&IOMUXC_PTD22), - (uint32_t)(&IOMUXC_PTD21), - (uint32_t)(&IOMUXC_PTD20), - (uint32_t)(&IOMUXC_PTD19), - (uint32_t)(&IOMUXC_PTD18), - (uint32_t)(&IOMUXC_PTD17), - (uint32_t)(&IOMUXC_PTD16), - (uint32_t)(&IOMUXC_PTD0), - (uint32_t)(&IOMUXC_PTD1), - (uint32_t)(&IOMUXC_PTD2), - (uint32_t)(&IOMUXC_PTD3), - (uint32_t)(&IOMUXC_PTD4), - (uint32_t)(&IOMUXC_PTD5), - (uint32_t)(&IOMUXC_PTD6), - (uint32_t)(&IOMUXC_PTD7), - (uint32_t)(&IOMUXC_PTD8), - (uint32_t)(&IOMUXC_PTD9), - (uint32_t)(&IOMUXC_PTD10), - (uint32_t)(&IOMUXC_PTD11), - (uint32_t)(&IOMUXC_PTD12), - (uint32_t)(&IOMUXC_PTD13), - (uint32_t)(&IOMUXC_PTB23), - (uint32_t)(&IOMUXC_PTB24), - (uint32_t)(&IOMUXC_PTB25), - (uint32_t)(&IOMUXC_PTB26), - (uint32_t)(&IOMUXC_PTB27), - (uint32_t)(&IOMUXC_PTB28), - (uint32_t)(&IOMUXC_PTC26), - (uint32_t)(&IOMUXC_PTC27), - (uint32_t)(&IOMUXC_PTC28), - (uint32_t)(&IOMUXC_PTC29), - (uint32_t)(&IOMUXC_PTC30), - (uint32_t)(&IOMUXC_PTC31), - (uint32_t)(&IOMUXC_PTE0), - (uint32_t)(&IOMUXC_PTE1), - (uint32_t)(&IOMUXC_PTE2), - (uint32_t)(&IOMUXC_PTE3), - (uint32_t)(&IOMUXC_PTE4), - (uint32_t)(&IOMUXC_PTE5), - (uint32_t)(&IOMUXC_PTE6), - (uint32_t)(&IOMUXC_PTE7), - (uint32_t)(&IOMUXC_PTE8), - (uint32_t)(&IOMUXC_PTE9), - (uint32_t)(&IOMUXC_PTE10), - (uint32_t)(&IOMUXC_PTE11), - (uint32_t)(&IOMUXC_PTE12), - (uint32_t)(&IOMUXC_PTE13), - (uint32_t)(&IOMUXC_PTE14), - (uint32_t)(&IOMUXC_PTE15), - (uint32_t)(&IOMUXC_PTE16), - (uint32_t)(&IOMUXC_PTE17), - (uint32_t)(&IOMUXC_PTE18), - (uint32_t)(&IOMUXC_PTE19), - (uint32_t)(&IOMUXC_PTE20), - (uint32_t)(&IOMUXC_PTE21), - (uint32_t)(&IOMUXC_PTE22), - (uint32_t)(&IOMUXC_PTE23), - (uint32_t)(&IOMUXC_PTE24), - (uint32_t)(&IOMUXC_PTE25), - (uint32_t)(&IOMUXC_PTE26), - (uint32_t)(&IOMUXC_PTE27), - (uint32_t)(&IOMUXC_PTE28), - (uint32_t)(&IOMUXC_PTA7), -}; - /******************************************************************************* * API ******************************************************************************/ diff --git a/platform/drivers/src/gpio_vf6xx.c b/platform/drivers/src/gpio_vf6xx.c index 28d8cd1..5f9326c 100644 --- a/platform/drivers/src/gpio_vf6xx.c +++ b/platform/drivers/src/gpio_vf6xx.c @@ -50,6 +50,8 @@ void GPIO_Init(GPIO_Type* base, gpio_init_t* initStruct) uint32_t dir; uint32_t iomux_addr; + + configure_gpio_pin(initStruct->pin); /* * Only on Vybrid the input/output buffer enable flags * are part of the shared mux/conf register. -- cgit v1.2.3